SOC Integration Engineer

MatX•Mountain View, CA

4d•Onsite

About The Position

MatX is building the compute platform for AGI, developing vertically integrated full-stack solutions from silicon to systems, including hardware and software, to train and run the largest ML workloads for AGI. MatX is seeking SOC Integration Engineers to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. Successful candidates for these roles will be responsible for delivering performant and functionally accurate silicon for MatX products across compute, memory management, high-speed connectivity, and other key technologies.

Requirements

Proficiency in SystemVerilog and scripting languages such as Python or Perl to drive chip design RTL and associated flows.
Proven track record in integrating high-performance computing elements (CPUs, GPUs, accelerators) and high-speed interconnect standards like UCIE, while managing memory and logical functionalities within the SOC RTL.
Working knowledge of logical equivalency verification for SOC-level subsystem interfaces, collaborating with physical design teams to incorporate floorplan requirements into the RTL.
Management of memory wrapper generation, including the integration of DFT wrappers into Subsystem RTL.
Automation support for generating and configuring SOC RTL with user-defined Subsystems for Design Verification (DV) purposes.
Hands-on experience with AI-driven tools to architect automation for SOC integration and facilitate technical support for cross-functional implementation teams.
Hands-on experience with design synthesis, linting, clock & reset-domain-crossing, and timing constraint validation to ensure high-quality SOC sign-off.
Must be authorized to work in the United States and work from our offices in Mountain View Tuesdays-Thursdays.
Applicant's capacity to perform job functions in compliance with U.S. export control laws without obtaining a license from U.S. export control authorities.

Nice To Haves

Familiarity with emulation platforms and verification methodologies is highly desirable.

Responsibilities

Drive the evolution of MatX's silicon architecture-to-design methodology by engineering scalable solutions for the seamless integration of all Subsystems into a comprehensive full-chip SOC RTL design.
Partner with SubSystem owners within the Design team to facilitate block integration and spearhead the development of the System-On-Chip (SOC) Top-level RTL.
Implement advanced automation for SOC top-level RTL integration and build processes to enable on-the-fly generation of SOC top-level RTL.
Collaborate closely with the Full Chip owner on the Physical Design team to incorporate necessary RTL modules and feedthroughs/highways, ensuring alignment with chip-level floorplan connectivity requirements within the SOC RTL.
Establish robust clock and reset methodologies through cross-functional collaboration with system, architecture, design, and physical design teams.
Define and support SoC-level timing constraints, ensuring rigorous validation against Subsystem design and physical design requirements.
Provide technical support to package and board teams by defining SOC pin requirements and facilitating the generation of interposer netlists.