Silicon Product Engineer – Manufacturing

NVIDIA•Santa Clara, CA

1d•Hybrid

About The Position

NVIDIA’s Silicon Co-Design Group works across architecture, silicon, systems, and manufacturing to bring GPU, SoC, and CPU silicon programs from first power-on to high-volume production. The Silicon Product Engineer will join the Testability, Manufacturability, Reliability & Quality (TMRQ) team and help validate and implement SLT/BLT production diagnostics and test specifications for silicon features. The role includes verifying POR specifications and supporting post-silicon validation for complex semiconductor chips in a high-volume manufacturing environment. The engineer will work across hardware and software teams and Production Operations to develop effective test coverage, support productization and production release, and improve manufacturing workflows. The role emphasizes hands-on silicon bring-up and debugging, production test coverage, data analysis, and continuous improvement, including deliberate use of AI to accelerate work while managing risk.

Requirements

Bachelor’s or Master’s degree, or equivalent experience, in Microelectronics, Electrical, Electronic, or Computer Engineering, or an equivalent field.
At least 3 years of relevant industry experience in silicon post-silicon PVT validation and/or high-volume manufacturing testing for complex SoCs, GPUs, CPUs, or similar products.
Hands-on lab experience with silicon bring-up, lab debugging, shmoo analysis, VF characteristics, test content bring-up, and correlation to silicon characterization, yield, and coverage optimization.
Strong electrical engineering fundamentals and knowledge of device physics, silicon design, statistics, STA concepts, fault analysis, sampling, and computer architecture.
Strong data analysis skills, a learning attitude, and prior experience working with large volumes of data.
Good understanding of firmware and driver structures and their interaction with hardware.
Problem-solving, debugging, analysis, and logical reasoning skills demonstrated through examples.
Experience with Python, BASH, Linux, and scripting.

Nice To Haves

Prior understanding of manufacturing test strategy for a major silicon product such as a GPU, SoC, or CPU, from early planning through ramp to QS/production.
Exceptional work ethic and ability to elevate discussions to solve real problems.
Native use of AI tools to accelerate production testing and debugging workflows.
Experience with GPUs, CPUs, AI accelerators, or other large-scale SoCs, including exposure to the complexity and failure landscape of these products.
Experience supporting cross-functional alignment on production methodologies adopted by other teams in a high-volume manufacturing environment.

Responsibilities

Develop and implement closed-loop analysis of VF characteristics and POR expectations against production screens to improve manufacturing screening diagnostics quality.
Support VF/VMIN/VMAX/PVT specification validation and productization across Manufacturing teams and product segments.
Partner with hardware engineering teams, including silicon PVT design and characterization, IO design and validation, system feature owners, and SLT/BLT Production Operations, to define test coverage and constraints and determine SLT/BLT test conditions, content, and flows for high-volume manufacturing screens.
Support prototyping and fine-tune speed, power, circuits, yield, and quality to provide effective silicon coverage in the SLT socketed environment.
Support procedures for silicon correlation between production testing infrastructure and internal silicon characterization and diagnostics programs.
Coordinate, develop, and maintain SLT/BLT testing flows, applying silicon learnings and correlating them to design for shift-left improvements.
Initiate and drive process improvements and preventative actions through root cause analysis and data analytics.
Partner with software and platform teams to support and improve SLT testing infrastructure, debug controls, and data collection features for manufacturing screens.