Silicon Physical Design Engineer V
About The Position
Fresh Consulting is seeking a Silicon Physical Design Engineer V for a one-year contract with a likely extension of up to two years. The role is remote and requires working Pacific Time hours. The engineer will develop and maintain power-analysis flows, generate and manage simulation activity inputs, correlate RTL estimates with gate-level signoff results, and analyze power by block, hierarchy, and workload. The position also includes identifying power-reduction opportunities, automating flows and reporting, performing PPA optimization with Fusion Compiler, running and debugging ASIC flows, implementing selected blocks at RTL and UPF, and communicating findings to design teams. Compensation is $75 to $115 USD per hour, determined by factors including location, level, job-related knowledge, skills, and experience. Fresh Consulting offers employee benefits at 100%, including medical, PTO, holiday pay, and a 401(k) plan. The company is an equal opportunity employer and participating E-Verify company.
Requirements
- At least 10 years of experience as an ASIC Power Engineer, CAD Engineer, or Physical Design Engineer.
- Experience with power-estimation tools and synthesis, plus some physical design experience.
- Knowledge of power trade-offs in design and back-end implementation.
- Hands-on experience in scripting and data analysis.
- BS in Electrical Engineering, Computer Science, or equivalent experience.
Nice To Haves
- Hands-on production experience with Synopsys tools (PPRTL, PTPX/PrimePower, VCS, Verdi, DC, ICC, FC) and/or Cadence Joules or PowerArtist.
- Ability to debug simulation-to-power-flow issues end to end.
- Strong scripting skills in TCL, Python, and Excel-based scripting; experience with data post-processing tools, model fitting, data visualization, and analysis; comfort with Linux and large compute/job-scheduling environments.
- Experience in low-power design, tools, and methodologies, including UPF power-intent specifications.
- Silicon power characterization, including some IP/SoC-level power modeling or profiling experience.
- Interest or experience in machine-learning hardware for AR/VR products.
Responsibilities
- Set up and maintain PPRTL and PTPX power-analysis flows for average and time-based/peak power.
- Generate and manage activity inputs (FSDB, VCD, and SAIF) from RTL and gate-level simulations, including long-waveform and windowed analysis.
- Correlate RTL-level power estimates against gate-level signoff power and explain differences.
- Produce per-block, per-hierarchy, and per-workload power breakdowns; identify top power contributors and clock/datapath waste.
- Recommend and evaluate power-reduction opportunities, including clock-gating efficiency, datapath gating, memory power, and idle leakage.
- Automate flows and reporting with TCL, Python, and Make-based build systems, and integrate them into regression/CI.
- Document methodology and support design teams in interpreting results.
- Perform PPA optimization with Fusion Compiler.
- Perform RTL- and netlist-level power analysis.
- Post-process and script report log files for format conversion, data analysis, and information extraction.
- Set up, run, debug, and analyze reports from ASIC flows, including synthesis, physical design, power, and timing.
- Implement selected blocks at RTL and UPF.
- Document and communicate findings clearly.
Benefits
- Employee benefits at 100%, including medical, PTO, holiday pay, and a 401(k) plan.
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What This Job Offers
Career Level
Senior
