Silicon Engineering Manager

Accenture • Austin, TX

16h

About The Position

Accenture LLP has multiple openings for the position of Silicon Engineering Manager in Austin, TX, and the job duties are as follows: Contribute to the development of Gate Level Simulation (GLS) TestBench architecture and verification of ASIC design with provided Netlist by developing or enhancing TestBench, running simulation of testcase suites and debugging failures. Drive the definition of TestPlan for RTL design through design specification. Define, develop, and integrate testcases to successfully verify RTL design using SV/UVM/C/Python languages and methodology. Work closely with design and architect engineers to define, develop and integrate required TestBench developments required for the RTL functional verification. Define, develop, and integrate functional coverage in the TestBench following Coverage Driven Verification methodology. Contribute development of testcases in C language to verify CPU based transactions as per the TestPlan. Define, develop, and integrate random constraints that will generate random valid input stimulus during daily testcase regressions. Supervise team execution and collaborate with client engineers, vendors, and SoC/SS teams to deliver functional verification requirements in timely manner.

Requirements

• Must have a bachelor’s degree in Computer Science, Technology, Computer Information Systems, Computer Applications, Engineering, or related field, plus 5 years of progressive post-baccalaureate experience in the IT consulting industry.
• Must have 5 years of experience in each of the following: Utilizing Hardware Description Languages (HDL), including SystemVerilog and C; Utilizing verification methodology including Universal Verification Methodology (UVM); Scripting knowledge of Python, Unix, and YAML; Working with Gate Level Simulation; Leading a team of junior engineers and mentor them; Working with industry-standard simulation and debug tools, including VCS, Questa, or Verdi; Utilizing computer architecture concepts, including NoC, memories, AMBA bus protocols (AXI, APB, AHB), and cache systems; Integrating and configuring third party including, Synopsys, Cadence, Siemens and Verification IPs (VIPs) into TestBench; Collaborating across-teams, proactiveness, working in a fast dynamic environment, result oriented, and a great communicator; and Project planning experience including resource estimation, negotiating commitments and identifying dependencies.
• Must have willingness and ability to travel domestically approximately 80% of the time to meet client needs.
• Applicants for employment in the US must have work authorization that does not now or in the future require sponsorship of a visa for employment authorization in the United States.

Responsibilities

• Contribute to the development of Gate Level Simulation (GLS) TestBench architecture and verification of ASIC design with provided Netlist by developing or enhancing TestBench, running simulation of testcase suites and debugging failures.
• Drive the definition of TestPlan for RTL design through design specification.
• Define, develop, and integrate testcases to successfully verify RTL design using SV/UVM/C/Python languages and methodology.
• Work closely with design and architect engineers to define, develop and integrate required TestBench developments required for the RTL functional verification.
• Define, develop, and integrate functional coverage in the TestBench following Coverage Driven Verification methodology.
• Contribute development of testcases in C language to verify CPU based transactions as per the TestPlan.
• Define, develop, and integrate random constraints that will generate random valid input stimulus during daily testcase regressions.
• Supervise team execution and collaborate with client engineers, vendors, and SoC/SS teams to deliver functional verification requirements in timely manner.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Number of Employees: 5,001-10,000 employees