VP of Silicon Engineering

Anodize•San Francisco, CA

16h

About The Position

We're a well-funded ($250M+), stealth startup building a new computing platform based on a high-performance edge SoC on an advanced process node. Our V1 strategy is lean and aggressive: we license best-in-class IP from Arm and others, and partner with a tier-1 ASIC design service for backend execution and physical design. We need a VP of Silicon who won't let external partners grade their own homework. Your immediate job is to build the team to own the development of a world-class SoC architecture, negotiate and integrate cutting-edge IP, and aggressively manage our ASIC partner to ensure they deliver top-tier PPA. Long-term, your mandate is to lay the groundwork for taking on more silicon design responsibilities in future iterations, gradually transitioning us from an IP integrator to a full-stack custom silicon company.

Requirements

15+ years of engineering experience with multiple tapeouts on advanced process nodes. You deeply understand the physical and electrical characteristics of bleeding-edge manufacturing.
Proven track record of successfully driving complex SoCs through an ASIC design service. You know exactly where external partners cut corners and how to catch them.
Deep, systemic expertise in Arm architectures, interconnect fabrics, and performance analysis tooling.
5+ years directing silicon engineering organizations. You know how to start lean, recruit elite talent, and scale an organization as internal responsibilities expand.
You are comfortable holding partners accountable. You know how to extract the best possible support, IP deliverables, and custom implementations from large external organizations.

Responsibilities

Build the Core Team. For V1, you will hire a lean, elite internal team of performance architects, low-power circuit experts, system-level DV engineers, and bring-up specialists to validate the architecture and keep the ASIC partner on the path of excellence. You will also lay the structural groundwork for bringing more front-end design in-house in future iterations.
Drive System Architecture. You will own the overarching architectural strategy. You'll make the hard executive calls to balance strict power constraints with massive performance and memory bandwidth targets.
Challenge the Defaults. Relying on an ASIC partner's defaults leads to missed opportunities. You and your team will actively push back on implementation choices, interrogate timing closure strategies, and force custom mitigation efforts rather than accepting sub-optimal work.
Obsess Over Power and Performance. We have unyielding targets for performance and for both active efficiency and retention power. You will build a culture that models performance and runs traces early to ensure all bottlenecks are identified before RTL freeze and direct the evaluation of advanced low-power circuit techniques and adaptive voltage scaling (AVS) strategies.
Own the Lifecycle. Your responsibility spans from early IP evaluation through product integration. You will drive post-silicon validation, silicon characterization, and hardware debug strategy, ensuring the chip meets all PPA targets and integrates seamlessly with the broader hardware and system software teams.