Physical Design Engineer II (Silicon Engineering)

SpaceX•Sunnyvale, CA

About The Position

SpaceX is seeking a motivated, proactive, and intellectually curious engineer to work alongside world-class cross-disciplinary teams. In this role, you will be developing cutting-edge next-generation ASICs for deployment in space and ground infrastructures. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.

Requirements

Bachelor’s degree in electrical engineering, computer engineering or computer science
3+ years of professional experience working on RTL2GDSII physical design and/or physical design flow development

Nice To Haves

Experience with industry standard EDA tools including understanding of their capabilities and underlying algorithms
Knowledge of deep sub-micron FinFET and CMOS solid state physics
Understanding of CMOS digital design principles, basic standard cells their functionality, standard cell libraries
Understanding of CMOS power dissipation in deep submicron processes leakage/dynamic
Familiar with CMOS analog circuit and physical design
Basic knowledge of DFT/Scan/MBIST/LBIST and understanding of their impact on physical design flows
Good scripting skills (csh/bash, Perl, Python, TCL, Makefile etc.)
Self-driven individual with a can-do attitude, willing to learn, and an ability to work in a dynamic group environment

Responsibilities

Perform partition synthesis and physical implementation steps (e.g. synthesis, floorplanning, power/ground grid generation, place and route, timing, noise, physical verification, electromigration, voltage drop, logic equivalency and other signoff checks)
Develop/improve physical design methodologies and automation scripts for various implementation steps
Closely collaborate with the ASIC design team to drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL/design tradeoffs
Resolve design/timing/congestion and flow issues, identify potential solutions and drive execution
Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, electromigration and voltage drop