Signal and Power Integrity (SI/PI) Engineer (SMES)

L3Harris Technologies•Camden, NJ

10d•$93,341 - $156,188•Onsite

About The Position

The Signal and Power Integrity (SI/PI) Engineer ensures the electrical integrity of high-speed digital and analog signals across complex PCB designs and maintains clean, stable power delivery within defined performance specifications. The role applies SI/PI analysis methodologies and simulation tools to support the reliability and performance of advanced communication systems for National Security applications. The position is based on-site in Camden, New Jersey, and follows a regular 9/80 schedule, with every other Friday off.

Requirements

Active SECRET clearance.
Bachelor's degree in Electrical Engineering or a related field with at least 6 years of relevant experience, or a master's degree with at least 4 years of relevant experience.
Specialization in digital CCA design and SI/PI analysis using commercial tools such as HyperLynx or Ansys SIwave.
Understanding of transmission line theory, impedance matching, crosstalk, reflection, and jitter.
Ability to model and analyze high-speed interconnects.
Familiarity with PCB fabrication and materials and their effects on high-speed digital design.
Strong analytical, debugging, and problem-solving skills, including logic and PCB debugging.
Ability to collaborate with cross-functional teams, including Components Engineering, ECAD, PCB design, RF, mechanical, systems, software, and factory personnel.
Excellent written, verbal, and presentation skills, including the ability to communicate technical findings clearly.

Nice To Haves

Experience in aerospace or defense.
Experience using Xpedition, HyperLynx, Ansys SIwave, or HFSS.
S-parameter modeling experience.
Experience with industry standards such as JEDEC and IEEE.
Experience with Earned Value Management.

Responsibilities

Perform signal and power integrity analysis for PCB designs.
Analyze digital Circuit Card Assemblies (CCAs) using tools such as HyperLynx, HFSS, and SIwave.
Generate layout and stack-up guidelines to ensure compliance with timing and signal-quality specifications.
Develop and validate IBIS models for pre- and post-layout simulation.
Conduct power integrity analysis to minimize power rail noise, voltage droop, and power plane resonance.
Ensure power delivery network (PDN) stability across relevant frequency ranges, including target impedance analysis.
Optimize PCB interconnects for PCIe Gen 4/5, DDR4/5, and LPDDR4/5.
Model and analyze SERDES interfaces.
Participate in peer and formal design reviews and evaluate root causes of signal and power issues.
Validate and debug designs in the lab as required.
Work with layout engineers, applying knowledge of PCB stack-up and high-speed layout constraints.
Prepare technical documentation and reports describing SI/PI findings and recommendations.