Senior Yield Enhancement Engineer #9573

TSMC•USA-Arizona, AZ

1d•Onsite

About The Position

A job at TSMC Arizona offers an opportunity to work at the most advanced semiconductor fab in the United States. TSMC Arizona’s first fab will operate its leading-edge semiconductor process technology (N4 process), starting production in the first half of 2025. The second fab will utilize its leading edge N3 and N2 process technology and be operational in 2028. The recently announced third fab will manufacture chips using 2nm or even more advanced process technology, with production starting by the end of the decade. America’s leading technology companies are ready to rely on TSMC Arizona for the next generations of chips that will power the digital future. As a Senior Yield Enhancement Engineer, you will demonstrate a strong sense of reliability and enthusiasm and will possess an attitude that embodies our core values – Integrity, Commitment, Innovation, and Customer Trust. Multiple positions available.

Requirements

Master’s degree (or foreign equivalent) in Electrical Engineering, Material Science, Physics, or a related field plus 2 years of experience in a process, equipment or integration semiconductor engineering role.
1 year of experience studying recipes in at least one of the following defect inspection metrologies used in the semiconductor industry: Bright Field (BF) inspection tool, Dark Field (DF) inspection tool, or Electron Beam Inspection (EBI) tool.
1 year of experience in at least one of the following defect review metrologies used in the semiconductor industry: Scanning Electron Microscopy (SEM), Critical Dimension SEM (CD-SEM), or Transmission Electron Microscopy (TEM).
Experience working in an ISO 4 (Class 10) or lower cleanroom environment.
Experience in at least 1 of the following: semiconductor physics, CMOS device operation, or advanced semiconductor manufacturing.
Experience with 2 of the following processes, including relative tool structure and process mechanism: LIT, ETC, WET, CVD, PVD, DIF, and CMP.
Willing and able to work on-site at our Phoenix Arizona facility.

Responsibilities

Define an aggressive defect reduction roadmap, identify potential yield-limiting defect sources, and collaborate with all internal departments, including integration, process engineering, and manufacturing, to optimize manufacturing processes.
Become the metrology tool and recipe owner, setting up and optimizing inline inspection and review recipes to enhance the capability for inline defect detection.
Utilize these tools to monitor and detect integrated and process tool shifts in a high-volume advanced semiconductor manufacturing fab.
Resolve issues and ensure proper escalation processes are followed.
Provide production line guidance and utilize statistical process control principles to sustain production line health and prevent defect-induced excursion events.
Coordinate with process engineers to identify and eliminate process and station defect sources, design and execute experiments, and interpret and extract insightful results from complex data sets to implement solutions promptly.
Serve as the project owner to coordinate overall yield improvement, defect reduction, quality enhancement, and new process technology qualification.