Senior Product, Test and Yield Enhancement Engineer - Taiwan

Cerebras Systems•Sunnyvale, CA

1d•Onsite

About The Position

Cerebras is seeking a senior VLSI product and test engineer with 10+ years of experience in semiconductor testing, failure analysis and yield enhancement. In this role, you will drive the test strategy for future generations of the Cerebras Wafer Scale Engine in Taiwan. Your work will span AI processors, high-speed I/O and memory; including ATE test development, manufacturing-data analysis, wafer disposition, defect characterization, failure isolation and yield improvement.

Requirements

BS or MS in Electrical Engineering, Computer Engineering or a related field.
10+ years of semiconductor product or test-engineering experience supporting highly integrated devices.
Strong experience in test development, silicon debug, test optimization and yield improvement.
Experience testing large parallel processors, GPUs, CPUs or networking ASICs incorporating SRAM, DDR/DRAM or HBM.
Expert-level, hands-on experience with the Advantest V93000 platform; Teradyne experience is a plus.
Experience specifying, designing, developing and debugging load boards and probe cards for advanced production-test and DFT requirements.
Strong cross-functional collaboration and problem-solving skills.
Experience working with Git-based development and release flows.

Nice To Haves

Programming experience with C, C++, Python or Perl for large-scale test-data analysis.
Experience with semiconductor test and failure-analysis tools or techniques such as Tessent, OBIRCH, IREM and LADA.
Experience testing high-speed SerDes at the ATE, package or system level.
Experience with analog blocks embedded within large digital ASICs.
Experience applying advanced data-analysis or machine-learning techniques to yield optimization.
Knowledge of wafer-scale packaging, TSVs, advanced interconnects, in-line diagnostics and defect-mitigation techniques.

Responsibilities

Develop and optimize production test programs for wafer-scale AI processors.
Drive high-volume manufacturing testing in partnership with foundries and outsourced semiconductor assembly and test providers (OSATs).
Implement and optimize design-for-test strategies, including scan, built-in self-test (BIST), automatic test-pattern generation (ATPG) and functional testing.
Analyze automated test equipment (ATE), Shmoo, parametric and defect data to improve yield and fault tolerance.
Develop failure-analysis and fault-isolation methods for defective cores, tiles and other functional blocks.
Build efficient wafer-level test flows for massively parallel compute, mesh and network-on-chip architectures, and die-to-die interconnects.
Partner closely with DFT, architecture, design, performance, software and manufacturing teams.
Optimize voltage-frequency operating limits, current, thermal behavior, power delivery and parallel die-testing capabilities.
Support wafer and lot disposition decisions throughout high-volume manufacturing.