Senior Staff SI/PI Engineer
About The Position
As an SI/PI, Package and Power Delivery Engineer at Tylsemi, you will own signal integrity, power integrity, and package/PDN co-design across chip, package, and board interfaces. You will work closely with SoC, physical design, analog, package, board, and validation teams to ensure robust high-speed links, stable power delivery, and predictable signoff from early architecture through tapeout and bring-up. The role is suited to engineers who enjoy cross-domain problem solving and translating complex electrical constraints into clean, manufacturable solutions. You will drive SI/PI planning and execution, model and analyze high-speed channels, own PDN design and analysis, and partner with design and package teams on architecture and signoff. You will also support lab bring-up and model correlation, develop automation and reporting, and contribute to tapeout readiness through documentation, reviews, and root-cause analysis.
Requirements
- 10+ years of hands-on experience delivering SI/PI and package/PDN solutions for complex SoCs, with scope aligned to level of experience.
- Strong fundamentals in transmission lines, S-parameters, impedance, return paths, coupling/crosstalk, and power delivery behavior across frequency.
- Ability to translate system requirements into actionable constraints and drive closure across multiple teams and design stages.
- Methodical debugging skills, including clear problem statements, data-driven root cause, and practical mitigation plans.
- Strong communication and engineering hygiene, including reproducible analyses, clean documentation, and review-friendly deliverables.
- Experience with signal integrity analysis for high-speed interfaces.
- Experience with power integrity and PDN design and analysis across chip, package, and board.
- Experience with package and power delivery co-design, including substrate/ballout/bumps, stackup, and routing constraints.
- Experience with electrical modeling, including S-parameters, SPICE, and IBIS/IBIS-AMI, and a correlation mindset.
- Ability to execute cross-functionally with SoC, physical design, analog, package, board, and validation teams.
Nice To Haves
- Experience with industry tools for SI/PI and package analysis, such as HFSS, SIwave, ADS, HSPICE/Spectre, PowerSI, Clarity, Ansys RedHawk/Voltus, or equivalents.
- DDR/LPDDR and SerDes compliance experience, including channel budgets, jitter/noise decomposition, and margining.
- Advanced packaging exposure, such as 2.5D/3D, interposers, chiplets, HBM, or CoWoS/EMIB-like concepts, and related SI/PI challenges.
- Thermal awareness in PDN/package decisions and collaboration with thermal/mechanical teams.
- Experience defining signoff criteria, templates, and reusable flows across programs.
Responsibilities
- Drive SI/PI methodology and execution from early planning through signoff for high-speed interfaces and power delivery networks.
- Perform package, board, and chip co-design, defining stackups, routing constraints, via strategies, reference planes, and return-path integrity.
- Model and analyze high-speed channels, including insertion and return loss, crosstalk, jitter, eye margins, and equalization tradeoffs.
- Build and validate electrical models, including IBIS/IBIS-AMI, S-parameters, and SPICE models, and ensure model correlation and version control hygiene.
- Own PDN design and analysis across die, package, and board, including impedance targets, decap strategy, anti-resonance mitigation, and rail stability.
- Run PI signoff, including DC/AC IR drop, EM, dynamic droop/noise, and power/ground bounce; drive fixes with clear, reviewable action plans.
- Partner with physical design and signoff teams on power grid architecture, bump/ball planning, current density limits, and rail partitioning.
- Collaborate with package engineering on substrate routing, escape, ballout, and manufacturability constraints; review and approve package design deliverables.
- Define and enforce design rules and constraints for routing, spacing, shielding, length matching, and reference plane transitions.
- Support lab bring-up and correlation by translating silicon, package, and board measurements into model updates and design improvements.
- Create and maintain automation, checks, and reporting using Python, Tcl, or equivalent tools to improve predictability, repeatability, and execution speed.
- Contribute to tapeout readiness through documentation, checklists, design reviews, and root-cause analysis to prevent recurrence.
Benefits
- Equity in the form of stock options.
Stand Out From the Crowd
Upload your resume and get instant feedback on how well it matches this job.
What This Job Offers
Job Type
Full-time
Career Level
Senior
Education Level
No Education Listed
