Senior Software R&D Engineer, ECO Route - VLSI EDA

NVIDIA•Austin, CA

About The Position

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. NVIDIA's world-leading hardware relies on design exploration beyond the limits of conventional tools. Our team develops highly optimized internal EDA technology by combining novel algorithms, parallel computing, machine learning, and high-performance C++. We are seeking a Senior Software R&D Engineer to invent the next generation of detailed physical design algorithms, with a focus on ECO routing and physical optimization. These algorithms sit at the core of applications spanning extreme timing and power optimization, incremental logic synthesis, metal ECOs, precision clock-tree tuning, and high-speed interconnect.

Requirements

MS, PhD, or equivalent experience, with 5+ years of relevant experience.
Strong expertise in C++, high-performance software architecture and algorithm development, including complexity, data structures, and memory efficiency.
Deep understanding of detailed routing, including advanced design rules, pin access, route optimization, and DRC-aware implementation.
Understanding of areas often impacted and co-optimized with ECOs, including clock distribution, DFT, and power delivery.
Authorization to work on export controlled data arising in CPUs, GPUs, LPUs, and communication networks.

Nice To Haves

Familiarity with logic and physical co-optimization principles, including logic restructuring, technology mapping, and using SAT solvers.
Experience with related physical-design areas such as placement, legalization, and IR drop reduction.
Experience applying LLMs, reinforcement learning, GNNs, or other machine-learning techniques to physical design, combinatorial optimization, or algorithm-performance tuning.

Responsibilities

Develop incremental physical-design technology that can rapidly implement high-performance logic changes with DRC and parasitic awareness, including for both all-layer and metal-only ECOs.
Invent improved detailed-routing algorithms for the intricate mix of discrete and continuous optimization problems arising from DRC constraints in the latest manufacturing processes.
Help craft cross-domain optimization tools that simultaneously consider logic, timing, clocks, testability, power distribution, placement, along with routing and DRCs to push the frontier of computing performance.
Own problems end-to-end—from algorithm invention through implementation, validation, and production deployment.