Join Ericsson’s Accelerator IP team in Austin, TX as a Senior RTL Design Engineer and own the microarchitecture of next-generation L1 accelerators from blank page to silicon. This role is for individuals who thrive on translating complex DSP/FEC algorithms into high-performance SystemVerilog, making tough power/area/throughput trade-offs, and delivering end-to-end IP in a lean, high-impact team. At Ericsson’s Accelerator IP team, we’re designing custom microarchitecture accelerators for EMCA L1 processing that push the boundaries of performance and innovation. You’ll work in a small, elite team where your ideas shape products used worldwide and your contributions have a direct line to impact. You’ll own major blocks end-to-end, from concept to final hand-off. This is an arena for those who thrive on turning complex algorithms into cutting-edge hardware and enjoy the adrenaline of building something from the ground up.
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Job Type
Full-time
Career Level
Senior
Education Level
No Education Listed