Join Ericsson’s Accelerator IP team in Austin, Texas, as a Senior RTL Design Engineer developing custom microarchitecture accelerators for EMCA L1 processing. The role owns major IP blocks from initial specification and microarchitecture through RTL creation, synthesis, and delivery, translating complex DSP, FEC, and other L1 processing algorithms into high-performance hardware. The engineer makes design trade-offs among power, area, and throughput and works closely with verification, backend/physical design, and architecture teams. The position is described as hybrid with on-site work and offers autonomy and technical impact in a small, close-knit team.
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Job Type
Full-time
Career Level
Senior
Education Level
No Education Listed