Principal ASIC Engineer

Echodyne Corp•Kirkland, WA

2d•$164,594 - $246,788

About The Position

Echodyne is seeking a Principal ASIC Engineer to join its Analog/Mixed-Signal (AMS) Engineering team and lead development and lifecycle support of custom integrated circuits for advanced radar products. The role serves as Echodyne’s ASIC subject-matter expert, providing hands-on technical leadership across the silicon development lifecycle. This includes supporting the manufacturability and long-term continuity of existing devices, and establishing the design methods, tool flows, and technical foundation for future in-house ASICs, from product definition through production release. The role combines deep IC-design expertise with Principal-level technical judgment, leadership of external partners, and an understanding of semiconductor economics. The position is exempt. Applicants must be evaluated for eligibility to handle U.S. Government export-controlled information or obtain required authorizations.

Requirements

Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related technical field and at least 15 years of relevant ASIC-development experience, or an equivalent combination of education and industry experience.
Proven record of delivering production ASICs across the complete development lifecycle, including successful tape-outs, silicon bring-up, and productization.
Broad knowledge of analog, digital, and mixed-signal ASIC development, with deep design expertise in at least one domain and sufficient breadth to lead integration and sign-off across a complete device.
Experience managing foundry, process-node, package, assembly, or test transitions for production ASICs, including technical risk assessment and requalification.
Strong understanding of semiconductor product engineering, including design for test, production test, post-silicon characterization, yield improvement, reliability qualification, and failure analysis.
Demonstrated success technically directing external ASIC design services and semiconductor suppliers against defined requirements, deliverables, quality expectations, and acceptance criteria.
Working knowledge of semiconductor cost structures and business models, with experience supporting make-versus-buy, sourcing, and commercial decisions.
Ability to work from broad direction, align technical execution with program and organizational priorities, make complex cross-disciplinary technical decisions, manage technical risks, and communicate recommendations clearly to internal teams and external partners.
Demonstrated ability to establish engineering methods, lead technical reviews, mentor engineers, and strengthen team capability through influence and collaboration.
Applicants will be asked during the application process to identify whether they are a U.S. citizen or green card holder, or have asylum/refugee status in the U.S., to assess eligibility to handle export-controlled information or obtain required Government authorizations.

Nice To Haves

Experience developing ASICs for radar, sensing, aerospace, defense, autonomous systems, or other high-reliability, long-lifecycle products.
Experience assuming technical ownership of an externally developed ASIC or transferring ASIC design knowledge and data between organizations.
Direct design experience across both analog or mixed-signal and digital IC domains.
Experience contributing to the establishment of new ASIC development flows, design environments, and external-partner operating models within a growing engineering organization.

Responsibilities

Own the long-term manufacturability, production continuity, and sustaining support of Echodyne’s existing ASICs.
Lead technical evaluation, qualification, and controlled release of foundry, process-node, package, assembly, test, and material changes; resolve related yield, reliability, quality, and obsolescence risks.
Work with Electrical Engineering, RF Engineering, and other stakeholders to translate product and system needs into ASIC requirements and architectures.
Lead ASIC functional partitioning and trade studies involving power, performance, area, process technology, intellectual property, packaging, test strategy, and make-versus-buy decisions.
Lead ASIC development from specification through production release, including analog, digital, and mixed-signal design; verification; physical implementation and sign-off; design for test; tape-out; silicon bring-up; characterization; qualification; and production ramp.
Define technical plans, review gates, risk mitigations, and readiness criteria throughout the development cycle.
Lead technical relationships with ASIC design partners, foundries, IP providers, EDA vendors, packaging suppliers, and OSAT providers; assess capabilities and proposals, define statements of work and acceptance criteria, review deliverables, and resolve technical issues.
Provide technical and cost inputs to ASIC sourcing decisions with Supply Chain, evaluating NRE, mask-set, wafer, yield, packaging, assembly, test, licensing, and production-volume economics to support supplier selection and commercial negotiations.
Establish ASIC design methods, review and sign-off practices, tool flows, data and configuration controls, and reusable development standards.
Preserve technical knowledge, mentor engineers, and help develop future ASIC capabilities within the team.