ASIC Engineer

Cisco•San Jose, CA

9d•$167,700 - $245,200

About The Position

Cisco Silicon One develops high-performance silicon ASICs used in complex networks, including data centers, service provider and enterprise networks. The team works on advanced IC package design and heterogeneous system integration, including substrates using 2.5D fanout technologies. The ASIC Engineer defines, designs, and owns ASIC subsystems from the front end through implementation for Cisco platforms. The role contributes to a multidisciplinary team working toward power, performance, and area goals, and helps define processes, methods, and tools for complex development. It involves developing high-frequency RTL, leading technical specifications and reviews, coordinating across engineering disciplines, and supporting debug from simulation through post-silicon validation.

Requirements

Bachelor's degree in Electrical or Computer Engineering and 7 or more years of ASIC design experience, or a master's degree in Electrical or Computer Engineering and 4 or more years of ASIC design experience.
ASIC design experience delivering silicon from microarchitecture, specification, and RTL coding through tape-out, including multiple tape-outs at advanced technology nodes.
Experience designing high-performance RTL using Verilog or SystemVerilog.
Understanding of timing closure, power optimization, and clock-gating techniques.
Experience with ASIC development flows, including simulation, synthesis, and static timing analysis.

Nice To Haves

Experience with documentation, problem-solving, and technical communication.
Experience working cross-functionally and collaborating with technical teams.
A self-starter who is highly motivated, enjoys solving new challenges, and thrives on innovative technology.
Enjoyment of dynamic team environments and an out-of-the-box approach to problem-solving.

Responsibilities

Define, design, and take end-to-end front-end ownership of ASIC subsystems for Cisco platforms.
Design and implement high-frequency, high-performance RTL in Verilog and SystemVerilog to meet timing, power, and area targets.
Lead design specifications and technical reviews, ensuring architectural clarity and high-quality implementation.
Drive technical execution across architecture, design, verification, and physical implementation teams.
Collaborate with verification and physical design teams to address functional coverage, timing, and integration challenges.
Mentor engineers and promote engineering rigor, design quality, and technical execution.
Lead debugging and root-cause analysis across simulation, system bring-up, and post-silicon validation.
Create reusable code that improves efficiency.
Influence system architecture and key design decisions across complex ASIC subsystems.
Help define processes, methods, and tools for complex design and implementation work.

Benefits

Medical, dental, and vision insurance.
401(k) plan with Cisco matching contribution.
Paid parental leave.
Short- and long-term disability coverage.
Basic life insurance.
Paid holidays and a floating holiday for non-exempt employees.
Paid birthday leave, year-end holiday shutdown, and personal wellness days.
Paid vacation or flexible vacation time off, depending on employee classification.
Sick time off.
Additional paid time away may be requested for critical or emergency family issues.
Optional paid volunteer days.
Annual bonuses for eligible non-sales roles.
Potential eligibility for Cisco restricted stock unit grants.