Senior Principal Design Verification Engineer

Renesas Electronics•Chandler, TX

About The Position

Renesas is seeking an experienced Principal Verification Engineer to lead verification efforts for its Automotive PMIC (Power Management Integrated Circuit) product line. The role combines mixed-signal verification expertise with leadership responsibilities, including mentoring junior engineers and driving verification strategy across multiple product platforms. The successful candidate will bring knowledge of analog, digital, and mixed-signal verification techniques and hands-on experience debugging automotive power management systems. The engineer will architect mixed-signal verification environments, develop verification plans for automotive PMIC products, establish and optimize gate-level simulation flows, and debug analog and digital design issues. The role also involves collaboration across design, application engineering, ATE, and silicon validation teams; improving verification methods and infrastructure; and maintaining verification documentation, test plans, and coverage. Renesas is an embedded semiconductor solution provider with more than 21,000 engineers and problem solvers in over 30 countries. Its culture is described by the values Transparent, Agile, Global, Innovative, and Entrepreneurial (TAGIE). The company states that it offers a competitive benefits package, with further information provided during the hiring process. Renesas is an equal opportunity and affirmative action employer. The company notes that its dual-use technology may be subject to U.S. export controls and that a government export license may be required before technology is released to certain persons.

Requirements

MS or PhD in Electrical Engineering, Computer Engineering, or a related field.
12+ years of experience in mixed-signal or analog circuit verification.
Deep understanding of mixed-signal verification environment architecture and implementation.
Hands-on experience with RNM and AMS model integration.
Proficiency with RTL and behavioral simulation tools such as Spectre and Xcelium.
Strong understanding of GLS flows and ability to set up and debug GLS simulations.
Experience debugging analog blocks such as switched-mode regulators, LDOs, bandgaps, and reference circuits, as well as digital RTL.
Experience with automotive PMIC or power management IC design and verification.
Proficiency in Verilog, SystemVerilog, and/or SPICE-based languages.
Understanding of UVM, assertions, and coverage-driven verification methodologies.
Experience interfacing with functional verification, post-silicon, and ATE test correlation domains.
Excellent problem-solving, debugging, and analytical skills.
Leadership and mentoring experience.

Responsibilities

Design and architect mixed-signal verification environments, including Real Number Model (RNM) and AMS model integration for PMIC designs.
Develop and implement verification plans and strategies for automotive PMIC products, ensuring compliance with automotive safety standards including ISO 26262 and AEC-Q200.
Set up and optimize Gate-Level Simulation (GLS) flows, correlating them with RTL simulation results to identify and resolve discrepancies.
Lead debugging activities for complex analog blocks, including switched-mode regulators, LDO regulators, and mixed-signal interfaces.
Conduct RTL and gate-level simulations, analyzing timing, power, and functional correctness across process, voltage, and temperature (PVT) corners.
Collaborate with Design, Application Engineering, ATE, and Silicon Validation teams to support verification handoffs.
Mentor junior verification engineers, define best practices, and establish verification methodologies.
Troubleshoot complex design issues involving interactions between analog and digital domains using simulation and measurement techniques.
Improve verification tools, methodologies, and infrastructure; evaluate emerging verification technologies and AI-based solutions.
Create and maintain verification documentation, test plans, and coverage.