Principal Design Verification Engineer

Microsoft•Redmond, WA

8d•$142,800 - $304,200

About The Position

Microsoft’s Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) team develops infrastructure and foundational technologies supporting Microsoft’s online services and Azure platform. Within SCHIE, the Artificial Intelligence System on Chip (AISoC) team helps define and deliver operational measures for hardware manufacturing, with a focus on planning, quality, delivery, scale, and sustainability. The team develops custom intellectual property and system-on-chip designs for complex, high-performance, and efficient functions. The Principal Design Verification Engineer will technically lead a pre-silicon verification team developing custom IP components. The role works with architects and design engineers to plan and execute verification, develop UVM components and testbench infrastructure, close functional coverage, debug failures, and provide technical leadership through mentorship and collaboration. The position requires Microsoft Cloud Background Check screening and eligibility to access information controlled under applicable export-control regulations. The role is listed as Silicon Engineering IC5. The typical U.S. base pay range is USD $142,800–$274,800 per year. For specific work locations in the San Francisco Bay Area and New York City metropolitan area, the range is USD $188,000–$304,200 per year. Certain roles may be eligible for benefits and other compensation. Applications are accepted on an ongoing basis until the position is filled; the posting will remain open for at least five days.

Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or a related field and 3+ years of technical engineering experience; or a master’s degree in one of these fields and 6+ years of technical engineering experience; or a bachelor’s degree in one of these fields and 8+ years of technical engineering experience; or equivalent experience.
Ability to meet Microsoft, customer, and/or government security screening requirements, including passing the Microsoft Cloud Background Check upon hire or transfer and every two years thereafter.
Provide proof of citizenship, U.S. permanent residency, or other protected status as required to assess eligibility to access export-controlled information; citizenship is verified with a valid passport, and applicable alternative documents may be used by lawful permanent residents, refugees, and asylees.

Nice To Haves

12+ years of experience in design verification.
Experience verifying multiple product cycles from definition to silicon, including writing test plans, developing tests, debugging failures, and coverage signoff in C++ and UVM.
Experience debugging RTL designs and simulation and/or emulation environments.
5+ years of experience in lead roles across cross-functional or cross-time-zone engineering teams.
Verification lead experience for an IP or subsystem related to CPUs, VPUs, GPUs, DMA engines, tensor units, or similar components.
Experience working on AI/ML SoCs.
Experience with a scripting language such as Python or Perl.
Hands-on experience in formal property verification.

Responsibilities

Technically lead a pre-silicon verification team developing custom IP components, focusing on architectural and micro-architectural functions and features.
Work with architects and design engineers to create test plans covering verification strategy, test requirements, and IP verification environments.
Write, execute, enhance, and debug constrained-random stimulus, scoreboards, checkers, and assertions to verify design correctness.
Develop Universal Verification Methodology (UVM) components that interface test code with verification simulation environments.
Collaborate across verification teams on vertical and horizontal reuse of components.
Define and implement functional coverage and drive coverage closure.
Triage and debug testbench, simulation, and emulation failures.
Write makefiles and scripts for verification infrastructure.
Apply Agile development methodologies, including code reviews, sprint planning, and feature deployment.
Provide technical leadership through mentorship and teamwork.