Principal Silicon Design Verification Engineer

Microsoft • San Diego, CA

8d • $142,800 - $304,200

About The Position

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) develops infrastructure and foundational technologies that power Microsoft’s online businesses and Azure platform. The team delivers server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions, with a focus on smart growth, high efficiency, and trusted customer and partner experiences.

The Principal Silicon Design Verification Engineer will functionally validate PCIe IP at the block, cluster, or full-chip level using UVM/C test benches and verification IP. The role includes developing test plans and unit tests, managing regression suites, debugging failures, and improving validation efficiency through methods and tools. The engineer is also expected to demonstrate Microsoft’s core values.

Requirements

• Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or a related field and 3+ years of technical engineering experience; or a master's degree in one of these fields and 6+ years of technical engineering experience; or a bachelor's degree in one of these fields and 8+ years of technical engineering experience; or equivalent experience.
• Ability to meet Microsoft, customer, and/or government security screening requirements, including passing the Microsoft Cloud Background Check upon hire or transfer and every two years thereafter.
• Must meet export-control eligibility requirements. The successful candidate must provide proof of citizenship, U.S. residency, or other protected status for assessment of eligibility to access export-controlled information; citizenship will be verified with a valid passport, with alternative documents applicable to lawful permanent residents, refugees, and asylees.

Nice To Haves

• Experience with protocol verification for PCIe, especially Gen6/Gen7, and related standards such as NVMe or RDMA.
• Experience with cluster, SoC, or full-chip-level verification.
• Prior PCIe verification experience at both the Transaction and Data Link Layers.
• Strong proficiency in Verilog, SystemVerilog, and UVM-based test bench environments.
• Good understanding of computer architecture and digital design fundamentals.
• Experience building UVM test benches, managing regressions, and meeting code coverage and functional coverage goals through successful tapeout.

Responsibilities

• Functionally validate PCIe IP at the block, cluster, or full-chip level using UVM/C test benches and verification IP (VIP).
• Develop test plans and write unit tests for functional validation.
• Create and manage regression suites, debug failures, and drive timely resolution.
• Innovate to improve validation efficiency through methodologies and tools.
• Demonstrate Microsoft core values: Customer Focus, Adaptability, Collaboration, Growth Mindset, Drive for Results, Influence for Impact, Judgement, and Diversity & Inclusion.

What This Job Offers

• Job Type: Full-time
• Career Level: Principal