Senior Power Integrity Engineer, Platforms Infrastructure

Google•Sunnyvale, CA
•$159,000 - $230,000

About The Position

As a Power Integrity Engineer within Platforms Infrastructure Engineering, you will develop power delivery network solutions for Google's computing infrastructure and next-generation AI hardware for AI/ML, server, networking, and storage applications. The role involves designing, analyzing, validating, and delivering solutions across chip, package, board, and rack levels, in collaboration with cross-functional teams. The team develops custom silicon and infrastructure supporting Google's products, AI models, cloud services, global networking, and hyperscale computing.

Requirements

  • Bachelor’s degree in Electrical Engineering, Computer Engineering, Physics, a related field, or equivalent practical experience.
  • At least 4 years of experience in a system-level power delivery network design, analysis, and validation technical environment.
  • Experience with PCB, package, and silicon technologies and their impact on power delivery solutions.

Nice To Haves

  • Master’s or PhD degree in Electrical Engineering, Computer Engineering, Physics, or a related field.
  • At least 1 year of experience in technical leadership.
  • Experience in board, substrate package, and on-chip power integrity and conversion design for FPGAs, ASICs, or high-performance processors.
  • Experience with industry-standard tools including Ansys HFSS, Q3D, and SIwave; Cadence PowerSI/DC, Allegro, and APD; CST; Keysight ADS; and Synopsys Hspice.
  • Experience in system-level PDN modeling, switching regulators, data center motherboard power design, advanced voltage regulators, and next-generation components.
  • Experience in die-to-PCB hardware validation and correlation, including scripting and automating lab measurements and EDA simulation workflows.

Responsibilities

  • Design system-level power delivery network solutions across silicon, substrate packaging, and printed circuit boards, partnering with cross-functional teams to balance performance, cost, reliability, and availability.
  • Perform power integrity design validation, correlation studies, and root-cause analyses; lead triage and resolution of power integrity issues.
  • Drive technology exploration into advanced power regulation and distribution across PCBs, chip packaging, and silicon.
  • Engage with power module suppliers and industry partners to develop and evaluate emerging power delivery technologies.
  • Collaborate with EDA vendors to enhance simulation capabilities and methodologies.

Benefits

  • 15% bonus target
  • Equity
  • Benefits
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