Senior Physical Design and Timing Engineer

NVIDIA•Durham, NC

7d•$136,000 - $264,500

About The Position

NVIDIA is seeking a Senior Physical Design and Timing Engineer to drive physical design and timing for high-frequency, low-power CPUs, GPUs, LPUs, and SoCs. The work may focus on block, cluster, and/or full-chip levels and includes helping drive implementation from RTL to GDSII. The engineer will collaborate across multiple teams in a cross-functional environment.

Requirements

Bachelor’s degree or equivalent experience in Electrical or Computer Engineering with at least 5 years of experience, or a master’s degree or equivalent experience with at least 3 years of experience in physical design, synthesis, and timing.
Strong hands-on experience taking complex blocks, IPs, or chips from RTL/netlist to tapeout, including logic synthesis, floorplanning, placement, clock-tree synthesis, routing, physical optimization, signoff, and ECOs.
Demonstrated success improving power, performance, and area through design improvements, critical-path planning and crafting, or methodology/workflow improvements.
Hands-on experience in block-, sub-chip-, and full-chip-level Static Timing Analysis, timing-constraint development, and multi-mode, multi-corner timing closure that accounts for process variations, IR drop, and crosstalk.
Expertise and in-depth knowledge of industry-standard EDA tools.
Proficiency in Python, Tcl, Perl, Make, or similar scripting languages, as well as AI/ML/DL/LLMs.

Nice To Haves

Physical design experience on high-performance CPUs, GPUs, LPUs, or AI accelerator designs.
Expertise or innovation in advanced physical design and circuit optimizations, clocking, or timing-closure strategies.
Experience developing scalable optimization and signoff solutions through automation or AI/Agentic frameworks.

Responsibilities

Drive physical design and timing for high-frequency, low-power CPUs, GPUs, LPUs, and SoCs at block, cluster, and/or full-chip level.
Help drive frontend and backend implementation from RTL to GDSII, including synthesis, equivalence checking, floorplanning, timing constraints, timing and power convergence, and ECO implementation.
Work in a cross-functional environment and interact with multiple teams.