Senior Hardware Electrical Engineer

Mercury Systems•Phoenix, AZ

About The Position

Mercury Systems is seeking a Senior Hardware Electrical Engineer to lead hardware and substrate design for rugged, high-reliability microelectronics used in defense, aerospace, and space systems. The position contributes to substrate and hardware design from concept through delivery, shapes engineering standards, guides complex technical decisions, and ensures reliability in harsh environments. The engineer works across sites and disciplines to develop microelectronic solutions supporting national security and onshore trusted manufacturing. The role provides technical leadership for complex System-in-Package (SiP) designs, including digital and RF packaged circuits, and supports microelectronics hardware development involving FPGAs, DACs, ADCs, storage devices, and other advanced components. It includes designing and analyzing high-speed interfaces, developing schematics and layouts using Cadence tools, and collaborating with layout and signal-integrity teams. The engineer also supports quality, manufacturing, testing, failure investigations, and proposal development. The position requires or may require a government security clearance, which is available only to U.S. citizens. Mercury describes a casual and enjoyable work atmosphere, opportunities to learn and grow, teamwork, communication and transparency, comprehensive skills training, and tuition reimbursement. Mercury Systems is an equal opportunity employer.

Requirements

Bachelor’s or higher-level degree in Electrical Engineering, Computer Engineering, or equivalent.
Typically requires a minimum of 4+ years of microelectronics packaging experience.
Experience leading microelectronics packaging efforts across cross-functional engineering teams.
Strong expertise in electronic circuit design, schematic capture, and troubleshooting across digital, analog, and power circuits.
Deep knowledge of high-speed digital design, signal-integrity fundamentals, IC package stack-ups, and advanced packaging techniques.
Experience working directly with substrate and interposer fabricators.
Experience mentoring junior engineers and leading engineering activities or small technical teams.
Must have or obtain a government security clearance; security clearances may only be granted to U.S. citizens.

Nice To Haves

Experience with FPGA-based designs using Intel (Altera) or AMD (Xilinx).
Experience working with high-frequency DACs and ADCs.
Development experience with embedded high-speed interfaces (25G+).
Proficiency with Cadence Allegro APD for layout analysis and design review.
Extensive understanding of signal-integrity principles for high-speed digital designs.
Understanding of RF design fundamentals for microelectronic applications.
Experience using requirements-management or collaboration tools such as JAMA, JIRA, or Confluence.
Familiarity with DFM, DFT, DFR, and cost-conscious design methodologies.
Experience supporting proposals, cost and schedule estimates, and Basis of Estimate (BOE) development.
Active DoD Secret Clearance or the ability to obtain one.

Responsibilities

Provide technical leadership to architect and develop complex System-in-Package (SiP) designs from concept through production.
Manage the design of microelectronic digital and RF packaged circuits that meet system and customer requirements.
Execute microelectronics hardware development involving FPGAs, DACs, ADCs, storage devices, and other advanced components.
Design and analyze high-speed digital interfaces, including Ethernet, PCIe, DDR, SATA, and USB.
Lead design quality activities through peer reviews, verification practices, and rigorous testing to minimize integration risk.
Coordinate with manufacturing and test teams to resolve build issues, support DFM/DFA/DFT efforts, and participate in detailed failure investigations.
Develop schematics and layouts for SiPs using Cadence toolsets and collaborate with layout and signal-integrity teams.
Provide hands-on support during SiP layout and perform signal-integrity analysis to ensure robust high-speed performance.
Support proposal development by contributing technical architectures, cost and schedule estimates, and Basis of Estimate (BOE) inputs.
Mentor junior engineers and lead engineering activities or small technical teams.