Senior FPGA Verification Engineer

Anduril • Waltham, MA

2d

About The Position

The Anduril Imaging team develops imaging systems spanning hardware and software, using computer vision, perception, electro-optical, infrared, and sensor data to address security challenges. The team is seeking a Senior FPGA Verification Engineer to help design new product lines. The role works with an interdisciplinary technical team to define and complete design and analysis, build prototypes for ground and flight testing, and mature prototypes into products. The position also provides technical leadership for project verification teams.

Requirements

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field is typically required.
• At least 8 years of experience developing HDL firmware for FPGA devices.
• Demonstrated experience developing and simulating RTL designs using VHDL and/or Verilog in a professional FPGA or ASIC development environment.
• Ability to design, implement, and execute verification testbenches for RTL blocks using VHDL and/or SystemVerilog.
• Experience with chip-level verification methodologies, including constrained-random testing, functional coverage analysis, and assertion-based verification using SystemVerilog.
• Experience using revision control systems such as Git or Subversion to manage source code, collaborate across engineering teams, and maintain configuration integrity.
• Eligible to obtain and maintain an active U.S. Secret security clearance.

Nice To Haves

• Experience with ASIC/FPGA lab validation and debug using standard lab equipment.
• Familiarity with DFT, manufacturability, and production test concepts.
• Proficiency with Unix/Linux environments.
• Scripting or software development experience in C, C++, Python, Perl, or shell.
• Experience with industry-standard ASIC/FPGA simulation and synthesis tools such as QuestaSim, Synplify, Quartus, or Vivado.

Responsibilities

• Architect and design verification environments using tools such as SystemVerilog or OVM/UVM.
• Create written test plans and test cases, and track code and functional coverage.
• Develop testbenches to verify RTL blocks using VHDL or SystemVerilog.
• Recommend tools and practices to continuously improve the group's ASIC/FPGA verification flow.
• Contribute engineering estimates for new program pursuits.
• Provide technical leadership for project verification teams by breaking down work, planning activities, and reporting status.
• Collaborate with an interdisciplinary technical team on design and analysis, prototype development, ground and flight testing, and product maturation.

Benefits

• Highly competitive equity grants are included in the majority of full-time offers and are considered part of Anduril's total compensation package.
• Top-tier benefits for full-time employees, described as comprehensive and competitive and available at little to no cost to employees.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior