Sr. FPGA Engineer

QuEra Computing•Boston, MA

About The Position

QuEra Computing is seeking a Senior FPGA Engineer to design, implement, and optimize high-performance FPGA systems for neutral atom quantum computing. The role focuses on real-time control systems, high-speed data acquisition, and precision timing systems that support quantum computer operation, including systems that manipulate individual atoms with microsecond precision. The engineer will develop SystemVerilog modules for quantum control, implement and integrate FPGA designs on Xilinx Zynq UltraScale+ RFSoC platforms, and build interfaces for high-speed data conversion and serial communications. The role also includes verification, performance optimization, reliability engineering, and troubleshooting hardware-software integration. The engineer will collaborate with physicists, software engineers, and system architects. Example projects include multichannel RF tone generation for quantum gates, real-time atom-detection image processing, synchronized control sequences, high-speed measurement data capture, and coordination across multiple boards. Success is measured by design quality, real-time performance, reliability, innovation, and effective cross-functional collaboration. The posting describes equity grants for new hires and emphasizes the opportunity to work on quantum computing systems; it does not specify a salary range.

Requirements

  • At least 5 years of FPGA development experience with Xilinx UltraScale+ devices.
  • Expert-level SystemVerilog knowledge and experience with modern verification methodologies.
  • Experience with high-speed serial protocols such as Aurora, AXI4, PCIe, or Ethernet.
  • Experience designing real-time systems with microsecond timing requirements.
  • Experience implementing digital signal processing in FPGAs.
  • Experience designing and verifying clock-domain crossings.
  • Python programming skills for test automation and data analysis.
  • Bachelor’s or master’s degree in electrical engineering, computer engineering, or physics.
  • Strong problem-solving skills and attention to detail.
  • Excellent communication skills for technical documentation and team collaboration.

Nice To Haves

  • Experience with RF or microwave systems, including frequency synthesis and phase-locked loops.
  • Experience with high-speed ADC/DAC interfaces, JESD204B/C, or RFSoC.
  • Experience with image-processing algorithms such as centroid detection or pattern recognition.
  • Experience with formal verification using SystemVerilog assertions.
  • CoaXPress or camera-interface experience.
  • Experience with AWS or cloud development environments.
  • Familiarity with High Level Synthesis and Vivado block design.
  • Experience with quantum computing, RF systems, or precision instrumentation.

Responsibilities

  • Design and implement SystemVerilog modules for quantum control systems, including scheduled multitone generators, real-time pulse sequencers, high-speed ADC/DAC interfaces, and hardware-accelerated image processing.
  • Develop and maintain FPGA designs for Xilinx Zynq UltraScale+ RFSoC platforms.
  • Implement high-speed serial interfaces, including CoaXPress, Aurora, and AXI4-Stream.
  • Design clock-domain crossing logic and perform CDC verification.
  • Optimize FPGA resource utilization and achieve timing closure for complex designs.
  • Create testbenches using SystemVerilog and Python tools such as cocotb.
  • Develop simulation models for quantum control peripherals.
  • Implement formal verification for critical timing constraints.
  • Design and validate real-time trigger and synchronization systems.
  • Troubleshoot hardware-software integration issues.
  • Optimize throughput for high-bandwidth quantum control signals.
  • Implement error detection and recovery mechanisms.
  • Design robust clocking architectures for multi-domain systems.
  • Develop system-health monitoring and diagnostics.
  • Ensure deterministic timing for quantum gate operations.
  • Propose and implement improvements to quantum control systems.
  • Produce clean, well-documented, maintainable SystemVerilog code and communicate effectively with cross-functional teams.

Benefits

  • Equity grants for all new hires
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