Principal/Sr. Principal FPGA Engineer

Northrop Grumman • Rolling Meadows, IL

3d • $119,600 - $223,900 • Onsite

About The Position

Northrop Grumman is seeking Principal and Sr. Principal FPGA Design Engineers for its Multidomain Sensing, Targeting, and Survivability Division in Rolling Meadows, Illinois. The division develops operational electronic warfare and targeting systems that provide situational awareness, self-protection, and electronic attack capability across visible-light, infrared, and millimeter-wave radio-frequency systems. Programs include military electronic warfare, communications, missile warning, infrared countermeasures, automatic test equipment, modeling and simulation, and situational awareness systems.

The engineer will contribute to end-to-end development of advanced RF and EO/IR products throughout the FPGA lifecycle: requirements analysis and refinement, system and FPGA architecture, RTL design, testbench development, verification, synthesis, implementation, timing closure, hardware integration, qualification, production support, and troubleshooting. The role develops FPGA-based digital subsystems integrated into circuit card assemblies and collaborates with systems, software, hardware, and integration and test engineers. Designs use technologies from vendors including AMD Xilinx, Intel FPGA, and Microchip, supporting high-speed interfaces, signal-processing chains, controls, data links, embedded processing, and processor interfaces.

The position is full-time and on-site in Rolling Meadows, Illinois, and may be filled at either the Principal or Sr. Principal level based on qualifications. Interim Secret clearance is required before starting, with the ability to obtain and maintain a Secret clearance afterward. U.S. citizenship is required. Travel is listed as 10% of the time, and relocation assistance may be available.

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a closely related engineering discipline with at least 5 years of relevant FPGA/ASIC design experience; or a master’s degree with at least 3 years of relevant experience; or a PhD with relevant experience (Principal level).
• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a closely related engineering discipline with at least 8 years of relevant FPGA/ASIC design experience; or a master’s degree with at least 6 years of relevant experience; or a PhD with at least 4 years of relevant experience (Sr. Principal level).
• Proficiency in VHDL, Verilog, or SystemVerilog for synthesizable RTL design.
• Experience developing synchronous RTL, including state machines, pipelined data paths, clock and reset architectures, and designs with multiple clock domains.
• Proficiency with the FPGA development flow, including RTL simulation, synthesis, place and route, static timing analysis, and power analysis.
• Experience with at least one major FPGA device architecture and its development toolchain, such as AMD Xilinx with Vivado or Intel FPGA with Quartus, and related EDA tools such as ModelSim/QuestaSim or Synplify.
• Experience using Python, Tcl, C/C++, or other scripting or programming languages for automation, verification, data generation, or report analysis.
• Ability to develop FPGA designs with minimal supervision, communicate status and risks proactively, participate in technical reviews, and work effectively across engineering disciplines.
• U.S. citizenship.
• Must have interim Secret clearance before starting and the ability to obtain and maintain a Secret security clearance.

Nice To Haves

• Current or active Secret or Top-Secret clearance with SCI/SAP eligibility.
• Domain knowledge in RF or EO/IR systems.
• Experience translating digital signal-processing or image-processing functions into efficient FPGA implementations.
• Experience with high-speed interfaces such as AXI, PCIe, Aurora, JESD, or 10G/25G/40G+ Ethernet.
• Experience with FPGA-based SoC architectures such as AMD Zynq/Versal or Intel SoC FPGA devices.
• Experience developing and integrating FPGA/software interfaces and controls.
• Experience developing or prototyping algorithms using MATLAB or Simulink.
• Experience using SystemVerilog/UVM, cocotb, or other structured verification frameworks.
• Experience with clock-domain-crossing and reset-domain-crossing analysis tools or methods.
• Experience developing physical and timing constraints from board schematics, electrical interfaces, and system timing requirements.
• Experience integrating vendor IP, embedded processors, memory controllers, high-speed transceivers, and board-level interfaces.
• Hardware troubleshooting experience using signal generators, logic analyzers, digital oscilloscopes, protocol analyzers, and embedded FPGA debug tools such as Vivado ILA or Intel SignalTap.
• Experience with FPGA power estimation, utilization analysis, and design optimization.
• Experience with configuration-management, requirements, planning, and review tools such as Git, SVN, ClearCase, DOORS, Jira, Rally, or ClearQuest.
• Experience supporting controlled or formal FPGA release, qualification, production, sustainment, and field-debug activities.
• Demonstrated technical leadership of complex FPGA developments from concept and architecture through implementation, verification, integration, qualification, and release.
• Experience independently resolving complex RTL, clock-domain-crossing, timing-closure, vendor-IP-integration, and hardware-debug issues.
• Experience leading FPGA requirements, architecture, detailed-design, test-readiness, or qualification reviews.
• Experience coordinating technical work across systems, software, hardware, verification, integration and test, manufacturing, and program-management teams.
• Demonstrated ability to communicate technical status, risks, tradeoffs, and recommendations to technical leadership and program stakeholders.
• Experience mentoring engineers, reviewing technical work products, and leading small technical teams.
• Ability to contribute to technical planning, estimates, risk mitigation, and proposal activities.
• Demonstrated adaptability, creativity, collaboration, initiative, and technical leadership in solving complex challenges and advancing technologies.

Responsibilities

• Contribute to requirements analysis and refinement, system and FPGA architecture, RTL design and coding, testbench development, verification, synthesis, implementation, timing closure, hardware integration, qualification, production support, and troubleshooting.
• Develop FPGA-based digital subsystems integrated into circuit card assemblies.
• Work with systems, software, hardware, and integration and test engineers.
• Translate system performance and operational requirements into FPGA architecture, detailed requirements, interfaces, implementation, and verification criteria.
• Develop and execute self-checking RTL test benches and requirements-based verification cases.
• Integrate and troubleshoot FPGA designs in simulation and laboratory hardware.
• For senior-level work, potentially define FPGA architecture, implementation strategy, interface definitions, and verification approaches; lead technical reviews and coordinate technical work across engineering teams; mentor engineers and contribute to planning, estimates, risk mitigation, and proposals.

Benefits

• Health insurance coverage
• Life insurance
• Disability insurance
• Savings plan
• Company-paid holidays
• Paid time off for vacation and/or personal business
• Potential overtime, shift differential, and discretionary bonus, depending on the position
• Relocation assistance may be available

What This Job Offers

• Job Type: Full-time
• Career Level: Principal