Principal FPGA Emulation Engineer

Renesas Electronics•Austin, TX

3d•Onsite

About The Position

Renesas is seeking a Principal FPGA Emulation & Prototyping Engineer to build and own FPGA-based platforms that emulate mixed-signal power ASICs before silicon. The role works closely with silicon RTL and DSP architects to bring designs up on FPGA and validate real-time digital, mixed-signal, and power-control architectures pre-silicon. The platforms are emulation vehicles rather than production hardware; success is measured by their fidelity to the target silicon, real-time or near-real-time performance for closed-loop power and DSP validation, and visibility for pre-silicon debug. The engineer adapts ASIC RTL for FPGA while preserving functional equivalence to the golden design, maps designs to FPGA resources and performance targets, and builds real-time environments around digital cores. This includes modeling or interfacing with analog and power stages, potentially using hardware-in-the-loop with real or emulated power hardware. The role also develops debug and visibility capabilities, supports firmware/software co-development ahead of silicon, improves emulation methodology and automation, and provides technical leadership across silicon and systems teams.

Requirements

Typically 10 or more years of extensive FPGA design and implementation experience, including a track record of FPGA prototyping or emulation of ASIC/SoC designs.
Expert-level RTL design in SystemVerilog and/or VHDL, with deep familiarity working from ASIC-style RTL.
Deep understanding of FPGA architecture and primitives, including DSP/multiplier slices, block and distributed RAM, carry chains, and clocking; ability to map large ASIC RTL to FPGA resources and achieve real-time emulation performance.
Hands-on experience adapting ASIC RTL for FPGA, including clock-gating conversion, memory macro replacement, reset schemes, tri-state conversion, and multi-clock/CDC handling.
Strong command of FPGA synthesis, place-and-route, timing analysis, and constraint development (XDC/SDC) on large Xilinx and/or Intel (Altera) devices using Vivado and/or Quartus.
Hardware bring-up and debug experience, including in-system logic analysis (ILA/SignalTap), lab instrumentation, and long-run pre-silicon debug.
Proficiency in automation scripting with TCL and Python.
Demonstrated technical leadership, including mentoring, reviews, and driving cross-team technical decisions.
BS or MS in Electrical Engineering, Computer Engineering, or a related field, or equivalent experience.

Nice To Haves

Real-time hardware-in-the-loop emulation and modeling of analog/mixed-signal and power stages, including ADC/DAC/PWM interfaces and plant/converter models.
Understanding of digital power-conversion control and mixed-signal systems, including converter topologies, control loops, PWM/PFM, and magnetics.
FPGA DSP implementation and real-time emulation of DSP datapaths such as FIR/IIR/CIC filters, interpolation/decimation, FFT, and FEC, including folding/unfolding techniques.
Experience with commercial FPGA prototyping platforms such as Synopsys HAPS, Cadence Protium, or Siemens Veloce.
Model-based design experience with Simulink and/or Xilinx System Generator.
High-speed interface experience with JESD204B, PCIe, 1G/10G Ethernet, or Aurora.
ASIC design or tape-out exposure, including DFT/scan considerations in emulation.
Ability to architect and build a custom in-house FPGA prototyping platform, including board architecture, high-speed PCB design, signal integrity, and bring-up.
Embedded/microcontroller and firmware co-development experience in C/assembly; MATLAB and C/C++.

Responsibilities

Partner with silicon RTL and DSP architects to bring ASIC designs up on FPGA, advise on FPGA-ability, and translate architectural intent into real-time emulation platforms.
Adapt ASIC RTL for FPGA emulation while preserving functional equivalence, including clock-gating conversion, memory/SRAM macro mapping, reset and initialization schemes, tri-state and bus conversion, and analog/mixed-signal block stubbing or modeling.
Map designs onto FPGA fabric to meet fit and emulation-speed goals by guiding resource inference, clocking, and pipelining.
Build real-time environments around digital cores by modeling or interfacing with analog and power stages, including ADC/DAC/PWM, gate drivers, and plant/converter models; use hardware-in-the-loop with real or emulated power hardware where needed.
Develop pre-silicon debug and visibility capabilities, including logic analysis, long-run waveform capture, triggering, and assertions.
Enable firmware and software co-development ahead of silicon.
Define and continuously improve emulation methodology, RTL/FPGA-ability guidelines, flows, and automation using TCL and Python.
Mentor engineers, lead reviews, and drive emulation and tooling decisions across silicon and systems teams.