Principal FPGA Emulation Engineer

Renesas Electronics•Austin, TX

About The Position

Renesas is seeking a Principal FPGA Emulation & Prototyping Engineer to build and own FPGA-based platforms that emulate mixed-signal power ASICs before silicon. The role works closely with silicon RTL and DSP architects to bring designs up on FPGA, validate real-time digital, mixed-signal, and power-control architectures, prove out control loops, identify RTL issues early, and reduce tape-out risk. The FPGA platforms are emulation vehicles rather than production hardware. Success is measured by how faithfully and quickly they reproduce target silicon, including functional equivalence to golden ASIC RTL, real-time or near-real-time performance for closed-loop power and DSP validation, and strong visibility for pre-silicon debug. The engineer will adapt ASIC RTL while preserving functional equivalence, map designs to FPGA resources and improve emulation speed, and build real-time environments around digital cores that interface with analog and power stages. The position also develops debug and visibility capabilities, supports firmware and software co-development before silicon, establishes emulation methods and automation, and provides technical leadership across silicon and systems teams. Renesas is an embedded semiconductor solution provider with a global team of more than 21,000 engineers and problem solvers in over 30 countries. Its stated purpose is to make lives easier, and its technology serves automotive, industrial, infrastructure, and IoT markets. The company describes its culture as Transparent, Agile, Global, Innovative, and Entrepreneurial, and states that it is an equal opportunity and affirmative action employer. The position may involve technology subject to U.S. export control regulations.

Requirements

Extensive FPGA design and implementation experience, typically 10 or more years, including a track record of FPGA prototyping or emulation of ASIC/SoC designs.
Expert-level SystemVerilog and/or VHDL RTL design, with deep familiarity working from ASIC-style RTL.
Deep understanding of FPGA architecture and primitives, including DSP/multiplier slices, block and distributed RAM, carry chains, and clocking, with demonstrated ability to map large ASIC RTL to FPGA resources and achieve real-time emulation performance.
Experience with memory/SRAM macro mapping, DSP inference, clock-enable conversion, and control-set and fanout management.
Hands-on experience adapting ASIC RTL for FPGA, including clock-gating conversion, memory macro replacement, reset schemes, tri-state conversion, and multi-clock/CDC handling.
Strong command of FPGA synthesis, place-and-route, timing analysis, and constraint development (XDC/SDC) for large Xilinx and/or Intel (Altera) devices using Vivado and/or Quartus.
Hardware bring-up and debug experience, including in-system logic analysis (ILA/SignalTap), lab instrumentation, and long-run pre-silicon debug.
Proficiency in TCL and Python scripting for automation.
Demonstrated technical leadership, including mentoring, reviews, and driving cross-team technical decisions.
BS or MS in Electrical Engineering, Computer Engineering, or a related field, or equivalent experience.

Nice To Haves

Experience with real-time hardware-in-the-loop emulation and modeling of analog/mixed-signal and power stages, including ADC/DAC/PWM interfaces and plant/converter models.
Understanding of digital power-conversion control and mixed-signal systems, including converter topologies, control loops, PWM/PFM, and magnetics.
FPGA DSP implementation and real-time emulation of DSP datapaths such as FIR/IIR/CIC filters, interpolation/decimation, FFT, and FEC, including folding/unfolding techniques.
Experience with commercial FPGA prototyping platforms such as Synopsys HAPS, Cadence Protium, or Siemens Veloce.
Model-based design experience with Simulink and/or Xilinx System Generator.
High-speed interface experience with JESD204B, PCIe, 1G/10G Ethernet, or Aurora.
ASIC design or tape-out exposure, including DFT/scan considerations in emulation.
Ability to architect and build a custom in-house FPGA prototyping platform, including board architecture, high-speed PCB design, signal integrity, and bring-up.
Embedded/microcontroller and firmware co-development experience using C/assembly; MATLAB, C, or C++ experience.

Responsibilities

Partner with silicon RTL and DSP architects to bring ASIC designs up on FPGA, advise on FPGA-ability, and turn architectural intent into working real-time emulation platforms.
Adapt ASIC RTL for FPGA emulation while preserving functional equivalence, including clock-gating conversion, memory/SRAM macro mapping, reset and initialization schemes, tri-state and bus conversion, and analog/mixed-signal block stubbing or modeling.
Map designs onto FPGA fabric to meet fit and emulation-speed requirements by managing resource inference, clocking, and pipelining.
Build real-time environments around the digital core and model or interface to analog and power stages, including ADC/DAC/PWM, gate drivers, plant/converter models, and hardware-in-the-loop where needed.
Develop pre-silicon debug and visibility through logic analysis, long-run waveform capture, triggering, and assertions.
Enable firmware and software co-development ahead of silicon.
Define and continually improve emulation methodology, RTL/FPGA-ability guidelines, implementation flows, and TCL/Python automation.
Mentor engineers, lead reviews, and drive emulation and tooling decisions across silicon and systems teams.