Sr FPGA Design Engineer (NetSec)

Palo Alto Networks•Office - USA - CA - Headquarters, CA

7d•$156,400 - $253,000

About The Position

Join Palo Alto Networks’ FPGA engineering team to deliver high-performance digital logic, CPLD/CFPGA modules, and hardware acceleration platforms for next-generation firewalls. The role owns FPGA design from architecture and specification through RTL development, timing closure, synthesis, and laboratory bring-up, working closely with software, hardware, and verification teams. The engineer will develop FPGA, CFPGA, and CPLD designs for advanced FPGA architectures, integrate complex high-speed IP, prototype and validate ASIC designs on FPGA platforms, and help pilot AI-driven design or verification workflows.

Requirements

Bachelor’s degree in electrical engineering, computer engineering, or computer science.
At least 5 years of FPGA/CPLD development experience.
Expertise in SystemVerilog and Verilog RTL development for FPGA and CPLD architectures.
Familiarity with simulation tools such as VCS and Questa for block-level verification.
Proven FPGA synthesis, placement, routing, and static timing analysis closure across multiple clock domains.
Scripting proficiency in Python, C/C++, Perl, bash, or tcsh.
Experience integrating and configuring high-speed IP cores, such as PCIe Gen4/5/6, DMA, Ethernet MAC/PHY, and memory controllers.
Experience with FPGA rapid prototyping, in-system logic debugging using tools such as ILA or SignalTap, and laboratory bring-up.
Ability to optimize resource utilization, including LUTs, FFs, BRAM/URAM, and DSP blocks, and apply timing-closure strategies.
Proficiency or active experience integrating modern AI tools into hardware design, scripting, or verification workflows.
Excellent leadership, collaboration, and written and verbal communication skills.

Nice To Haves

MSEE or equivalent military experience.
Experience with ASIC-to-FPGA prototyping flows and emulation environments.
Hands-on experience with high-density FPGA platforms such as AMD UltraScale+/Versal or Altera Agilex/Stratix.
Formal verification experience, such as VC Formal, applied to FPGA module verification.
Networking experience in Ethernet packet processing and CPLD/CFPGA board-management logic design.

Responsibilities

Write micro-architecture and functional specifications for FPGA, CFPGA, and CPLD designs.
Develop SystemVerilog and Verilog RTL for advanced FPGA architectures while meeting timing and power targets.
Synthesize and implement designs using Vivado, Quartus, and Synopsys tools; close timing across multiple clock domains and optimize resource use.
Prototype and validate ASIC designs on FPGA platforms, including laboratory bring-up, in-system debugging, and hardware validation.
Collaborate with software teams to define interfaces, review memory-map structures, and integrate IP blocks such as PCIe, Ethernet, DMA, and DDR/LPDDR.
Pilot AI-driven design or verification flows to reduce schedule risk.
Analyze timing, power, and area reports and drive corrective fixes.