FPGA Design Engineer

Quest Defense Systems & Solutions, Inc.•Phoenix, AZ

8d•$100,000 - $125,000•Onsite

About The Position

Quest Defense Systems & Solutions is seeking FPGA Design Engineers to support modernization of the T3CAS platform through firmware development that complies with DO-254 requirements. The role involves advanced FPGA design and safety-critical aerospace development. The existing certified design is being consolidated from multiple FPGA devices to a single device. Its internal pulse-decoding and transmission-sequencing logic is expected to remain largely unchanged, while interfaces will need to adapt to a new RF hardware architecture being developed by the ACSS team. Some HRD development may also be included. The engineer will develop RF FPGA design artifacts and a MATLAB model for assessing overall system performance. The model will cover the RF input chain and relevant FPGA data flow, using Simulink or other fixed-point models, and should be maintainable by ACSS. The role also supports IOC and PC PLD design and documentation, HTPR documentation development, verification and validation, and certification activities. The position is located in Phoenix, Arizona. Candidates must be U.S. citizens or U.S. persons. Quest Defense describes its environment as collaborative, flexible, and people-first, with purpose-driven work on mission-critical programs. Compensation is based on experience and certifications, with a listed pay range of $100,000–$125,000 USD.

Requirements

Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field.
3–6 years of experience in FPGA design and development, including digital logic design, FPGA implementation, and hardware interface integration.
Experience with FPGA verification and validation, including timing analysis, simulation, debugging, and technical documentation.
Experience with MATLAB/Simulink for system modeling, simulation, or performance analysis.
Experience with DO-254 or other safety-critical development standards.
Experience developing or modifying FPGA logic using VHDL or Verilog.
Experience supporting hardware certification, requirements traceability, design reviews, and verification documentation.
Must be a U.S. citizen or U.S. person.

Responsibilities

Develop RF FPGA design and artifacts for the T3CAS platform modernization, including adaptations for the new RF hardware architecture.
Develop a MATLAB model to assess overall system performance, covering the RF input chain and relevant FPGA data flow, and confirm that system performance requirements are met.
Support development of IOC and PC PLD designs and documentation.
Develop HTPR documentation for IOC, PC PLD, and/or RF FPGA, based on HRDs developed by ACSS and potentially previously developed HTPRs.
Support preparation and execution of verification and validation, including Static Timing Analysis, Multi-Cock Domain Analysis, and Fault Injection Analysis.
Work with ACSS engineering to resolve issues found during verification and validation.
Support certification activities, including DO-254 subject-matter work, code coverage, and inspections.