Senior Foundry Development Engineer

AttoTude•Menlo Park, CA

About The Position

AttoTude is a venture-backed startup that develops high-speed interconnect links using ASICs over dielectric waveguides. The Senior Foundry Development Engineer will own dielectric waveguide process development, from material selection through process development, and lead the transfer of qualified processes to internal fabs and external foundries. The role collaborates with product development, packaging, and foundry-interface teams, combining electrical engineering, surface science, and materials science knowledge with hands-on experimentation. The successful candidate will develop hypotheses, design and execute experiments, work with internal and external fabrication facilities, and turn experimental observations into performance improvements. The role also involves developing processes with partners and balancing engineering specifications with business partnership objectives in a startup environment. The annual salary range is $170,000–$250,000 USD.

Requirements

  • Master’s degree in Electrical Engineering or Materials Science; a PhD is considered ideal.
  • 10 or more years of hands-on silicon fabrication process engineering in a cleanroom environment.
  • Demonstrated expertise in semiconductor etching process development and tuning on production-class platforms.
  • Working knowledge of etch surface damage mechanisms, their characterization and mitigation, and how sidewall and surface condition affects downstream processing and device performance.
  • Familiarity with lithography, wet chemical cleaning, thermal oxidation, and semiconductor cleanliness and contamination control.
  • Proficiency with DOE, SPC, and failure analysis methods.
  • Clear written communication skills, including the ability to prepare process specifications and technical reports.

Nice To Haves

  • Track record of transferring processes to outside foundries or high-volume fabs, from specification and qualification through ongoing yield support.
  • Experience with through-silicon vias (TSVs), silicon interposers, MEMS, or SOI-based structures.
  • Exposure to RF, millimeter-wave, or THz devices, including dielectric waveguide structures.
  • Familiarity with wafer bonding, thinning, and dicing processes.

Responsibilities

  • Develop, optimize, and document RIE, Bosch, and cryogenic semiconductor etch processes for high-aspect-ratio structures, controlling etch rate, mask selectivity, profile angle, sidewall scalloping, uniformity, and aspect-ratio-dependent etching.
  • Characterize and mitigate etch-induced surface and subsurface damage, including sidewall roughness, notching and footing at buried layers, fluorocarbon polymer residue, and plasma-induced lattice damage.
  • Define post-etch treatments and work with the broader team to verify their effects on downstream metrics.
  • Establish metrology and inspection methods, including SEM cross-sections, AFM, profilometry, and optical inspection, and correlate surface condition with electrical and RF test results.
  • Identify, evaluate, and develop foundry partners by assessing technical capability, capacity, quality systems, and cost against AttoTude's product roadmap.
  • Build long-term business partnerships with foundries and suppliers, structuring development, qualification, and supply engagements that align with technical and commercial objectives.
  • Lead process transfers to outside foundries by writing process specifications and travelers, defining acceptance criteria and SPC limits, supporting qualification lots, and resolving yield excursions.
  • Serve as the technical point of contact for foundry and equipment partners, review vendor data, assess partner capability, and drive corrective actions.
  • Hold regular technical and business reviews with partners to track performance, align roadmaps, and resolve issues before they affect schedules.
  • Apply DOE, SPC, FMEA, and structured root cause analysis to process development and sustaining work.
  • Maintain process documentation and train colleagues and partner engineers on DRIE best practices.
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