Senior Design Verification Engineer

Intel•Santa Clara, CA

18h•Onsite

About The Position

Intel’s Unified Intel Chassis (UIC) team is a new IP development team focused on chassis and interconnect technology and a configurable generator for SoCs and chiplets. The Senior Design Verification Engineer verifies coherent, non-coherent, and I/O-coherent systems, including interactions among interconnects, caches, memory subsystems, and chassis functions such as clocking, power management, reset, debug, and trace. This is a hands-on technical role spanning the full verification lifecycle, from clarifying requirements and building models and checkers through debugging and verification signoff. The engineer works with architecture, design, verification, and tooling teams to turn specifications into working, tested hardware. Simulation, formal verification, and AI-assisted development are part of the team’s approach. The role calls for ownership of complex verification work through closure, cross-block root-cause analysis, collaboration across engineering disciplines, and clear communication of risks and evidence for verification closure. The position is on-site. The annual US salary range is $190,610 to $269,100, with individual pay determined by location and other job-related factors.

Requirements

BS or MS in Electrical Engineering, Computer Science, or a related field, with 10+ years of relevant design verification experience.
Background in IP design verification with significant subsystem- and SoC-level verification experience.
Hands-on experience verifying high-performance interconnects and memory subsystems, including coherent, non-coherent, and I/O-coherent operation, cache coherency, memory consistency, transaction ordering, virtual memory, IOMMUs, and interrupt controllers.
Experience with MESI/MOESI-based coherency mechanisms and protocols such as AMBA CHI, CXL, or comparable architectures.
SystemVerilog/UVM and assertion-based verification skills, with practical experience applying formal verification alongside simulation and understanding the limits of each method.
Programming and debugging skills in SystemVerilog and Python or C/C++; ability to read RTL, build independent reference models and checkers, and develop maintainable test automation.
Demonstrated ownership of complex verification work through closure, including cross-block root-cause analysis and clear technical communication across engineering disciplines.
Collaborative approach to working across architecture, design, and verification teams to define requirements, resolve ambiguity, and drive toward shared goals.
Rigorous, evidence-driven mindset that questions assumptions, independently validates generated work, and communicates risk clearly.

Nice To Haves

Experience with configurable interconnect generators, generated testbenches, and verification across topology, parameter, and multi-die configurations.
Experience with formal abstraction and proof decomposition, or emulation-based validation of system workloads.
Experience verifying clocking, power management, reset, debug, trace, RAS, security isolation, or QoS interactions at subsystem level.
Knowledge of cache hierarchies, home nodes, duplicate-tag structures, snoop filters, memory controllers, and how their interactions affect correctness and performance.
Experience building and evaluating AI-assisted engineering workflows, including checks for incorrect generated code, properties, or specification interpretations.

Responsibilities

Own verification plans for chassis and interconnect IP, prioritize functional and integration risks, and drive assigned features from initial bring-up through signoff.
Build reusable environments, reference models, and checkers for data integrity, ordering, address translation, access permissions, interrupt routing and delivery, and forward progress under concurrent traffic and backpressure.
Use simulation, formal properties, and targeted experiments to find bugs; review assumptions, checker completeness, coverage gaps, and proof results rather than relying only on passing regressions.
Collaborate with design and verification engineers to define interface contracts, share VIP and assertions, and debug interactions across data paths, clock and power transitions, reset sequences, and debug and trace functions.
Work with architecture, design, and tooling engineers to clarify specifications, evaluate tradeoffs, and contribute reviewed changes to models, RTL, and verification infrastructure.
Develop configuration-driven regressions and AI-assisted workflows for coding, property development, and debug; validate generated work with independent checks and reproducible tests across supported configurations.
Mentor engineers through code and testplan reviews, communicate remaining risks, and establish clear evidence for verification closure.