Senior Design Verification Engineer – CPU Core Verification (Vector)

SiFive•Austin, TX

About The Position

SiFive is looking for a Senior Design Verification Engineer to drive verification of high-performance CPU core functionality, with meaningful scope in RISC-V Vector Extension (RVV) and vector microarchitecture verification. This role is within the CPU Design Verification organization and focuses on high-performance out-of-order CPU core development. The scope includes core areas such as Frontend, Midcore, Load-Store Unit, Hardware Prefetch, and Vector Unit / vector microarchitectural interactions. We are looking for an engineer who can independently own meaningful verification work, create effective verification strategies and test plans, solve complex debug problems efficiently, and contribute reusable methodology and infrastructure to the broader CPU DV team. You will work closely with architecture, RTL, performance, and verification teams to ensure design intent is verified correctly, difficult corner cases are covered thoroughly, and signoff quality is achieved with strong technical execution.

Requirements

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
5+ years of relevant experience in IP, CPU/core, or SoC functional verification, preferably with direct experience in CPU/core verification.
Strong hands-on experience with SystemVerilog-based verification and modern verification methodologies.
Solid understanding of computer architecture and CPU microarchitecture fundamentals.
Experience with test planning, verification environment development, stimulus generation, failure analysis, coverage analysis, and coverage closure.
Strong debug skills and the ability to translate architectural intent into effective verification strategy and execution.
Strong programming and scripting fundamentals for building scalable verification solutions.
Experience in one or more CPU core areas such as Frontend, Midcore, Load-Store Unit, memory ordering and consistency, Hardware Prefetch, or Vector Unit verification.

Nice To Haves

Direct experience with high-performance out-of-order CPU core verification.
Experience with RISC-V Vector Extension (RVV), SIMD, or vector-processor verification.
Experience verifying vector behaviors such as vector arithmetic, masking, reductions, permutations, vector-scalar operations, and vector load/store functionality.
Experience verifying vector memory behavior, including alignment, page-boundary conditions, exception handling, hazard detection, cache/memory interactions, and coherency-sensitive scenarios.
Experience working with vector configuration and execution modes such as SEW, LMUL, VL, VSTART, and related legality / corner-case behavior.
Experience verifying complex CPU microarchitectural behaviors involving concurrency, replay, flush, redirects, dependency handling, or weak memory ordering.
Experience developing high-value assertions, checkers, and scoreboards for control-heavy or ordering-sensitive CPU behavior.
Familiarity with formal verification, emulation, or acceleration for high-risk or hard-to-observe verification problems.
Experience collaborating effectively with performance, compiler, system verification, and software teams to close verification gaps from multiple perspectives.

Responsibilities

Own verification planning and execution for assigned high-performance CPU core areas, from block-level verification through core-level integration.
Create effective verification strategies and test plans based on CPU architecture and microarchitectural behavior.
Develop and maintain robust verification environments, checkers, scoreboards, assertions, stimulus, and coverage models.
Define and execute directed and constrained-random tests that expose corner cases in branch prediction, instruction fetch, pipeline interactions, issue/dispatch behavior, hazard handling, load/store ordering, memory consistency, hardware prefetch behavior, and vector execution correctness.
Drive verification of RVV and vector-unit functionality, including vector arithmetic, vector memory operations, masking behavior, configuration-dependent execution, hazard handling, exception behavior, and scalar-vector interactions.
Verify vector microarchitectural behaviors involving SEW, LMUL, VL, VSTART, masking, vector register-file behavior, vector memory sequencing, and interaction with the scalar pipeline and cache / memory hierarchy.
Analyze failures, isolate root cause, and drive fixes across RTL, verification infrastructure, assertions, and test content.
Collaborate closely with architecture and design teams to review specifications, identify ambiguities early, and improve verification quality and debugability.
Write functional coverage, analyze code and functional coverage, and close coverage gaps to ensure verification completeness and signoff quality.
Contribute reusable DV methodology, automation, and infrastructure that improve team productivity and verification quality across future CPU core generations.