Engineer, CPU Performance Verification

Tenstorrent • Austin, TX

1d • Hybrid

About The Position

Tenstorrent is seeking an engineer to join its CPU design team and drive performance verification and correlation between RTL and the performance model. The role focuses on a CPU based on the RISC-V ISA, working closely with core architects and RTL teams to deliver an efficient, high-performance design. The position is hybrid and based in Austin, Texas, or Santa Clara, California. Candidates at various experience levels are welcome; candidates will be assessed during the interview process for an appropriate level, and offers will align with that level, which may differ from the level in the posting.

The engineer will help improve CPU microarchitecture, verify performance, and correlate RTL against the performance model. The role includes analyzing performance data, finding bottlenecks, debugging mismatches, creating performance test plans and microbenchmarks, and improving analysis and correlation tools and methods. The work also involves running performance experiments and evaluating approaches to optimize power, performance, and area.

The role provides exposure to CPU design from microarchitecture through performance convergence and validation, including optimization work in pre-silicon and post-silicon phases and the performance modeling and RTL simulation and emulation flows used to verify a high-performance CPU. Compensation ranges from $100,000 to $500,000, including base and variable compensation targets; the actual offer depends on experience, skills, education, background, and location. Employment is contingent on eligibility to access U.S. export-controlled technology, which may depend on citizenship or permanent-residency status or the ability to obtain required license approval.

Requirements

• Experience analyzing modern CPU performance data, identifying bottlenecks, and building tools to support efficient analysis.
• Proficiency in C++ and Python.
• Understanding of industry-standard tools for compilation, simulation, and emulation.
• Knowledge of high-performance CPU architecture and microarchitecture.
• Proficiency debugging RTL and logic across multiple design hierarchies and pre-silicon environments.
• Exposure to performance modeling and RTL-to-model correlation.

Responsibilities

• Drive performance verification and correlate RTL against the performance model.
• Collaborate with RTL engineers and core architects to meet performance goals, debug miscorrelation, and verify performance features.
• Draft performance test plans and develop targeted microbenchmarks to exercise performance features and expose bottlenecks.
• Enhance tools and methodologies for performance analysis and correlation to improve development efficiency.
• Conduct performance experiments, evaluate results, and use innovative techniques to optimize power, performance, and area.

What This Job Offers

• Job Type: Full-time
• Education Level: No Education Listed