Senior CPU Power Architect

NVIDIA•Santa Clara, CA

2d•$152,000 - $287,500

About The Position

NVIDIA is seeking a CPU Power Architect to optimize CPU power efficiency throughout the design cycle, from early architectural modeling through RTL implementation and silicon validation. The role partners with software, architecture, RTL, physical design, and validation teams to identify power-saving opportunities, inform design trade-offs, and help CPUs meet performance-per-watt goals. It applies expertise in power analysis, modeling, and optimization, using silicon data to validate assumptions and improve future designs. The role includes estimating CPU power at C-model, RTL, and netlist stages using industry-standard tools; driving design improvements; developing power characterization tests; and measuring CPU power and performance in the lab. NVIDIA's CPU architecture team develops CPUs that complement its GPUs and SoCs and support workloads such as AI training, data processing, and cloud deployments.

Requirements

BS/MS in EE, CE, or CS, or equivalent experience.
5+ years of experience working in ASIC power measurement and optimization.
Strong understanding of leakage and dynamic power in VLSI circuits.
Experience with RTL and netlist power analysis tools such as Power Artist, PrimeTime PX, or equivalent.
Familiarity with CPU microarchitecture and its impact on power, including CPU pipeline design, out-of-order execution, cache hierarchy, and branch prediction.

Nice To Haves

Proficiency in using AI tools for automation and data analysis.
Experience with DVFS, clock gating, power gating, and multi-voltage domain design.
Knowledge of lab instrumentation for power measurement.
Strong communication skills for cross-team technical discussions.

Responsibilities

Model and estimate CPU power at C-model, RTL, and netlist stages using industry-standard tools.
Identify power inefficiencies and drive design improvements with architects, RTL designers, and physical design engineers.
Create targeted power characterization tests, including peak-power and di/dt stress patterns, for simulation and silicon.
Set up power measurement equipment and measure CPU power and performance in the lab.
Correlate silicon results with pre-silicon estimates to refine power models.
Collaborate across engineering disciplines to improve power efficiency without compromising performance.