Senior CPU Power Architect

NVIDIA•Santa Clara, CA

About The Position

NVIDIA is seeking a CPU Power Architect to drive and optimize CPU power efficiency across the design cycle, from early architectural modeling through RTL implementation and silicon validation. The role works closely with software, architecture, RTL, physical design, and validation teams to identify power-saving opportunities, guide design trade-offs, and help CPUs meet performance-per-watt goals. It applies power analysis, modeling, and optimization expertise, using silicon data to validate assumptions and refine future designs. Strong communication and collaboration are important for influencing cross-functional teams and delivering efficient CPU products. NVIDIA’s CPU architecture team develops CPUs that integrate with its broader technology stack. The Grace and Vera CPU Superchips expand NVIDIA’s presence in the CPU server market and support workloads requiring high performance-per-watt efficiency, including AI model training, data processing, and cloud deployments.

Requirements

BS or MS in electrical engineering, computer engineering, or computer science, or equivalent experience.
At least 5 years of experience in ASIC power measurement and optimization.
Strong understanding of leakage and dynamic power in VLSI circuits.
Experience with RTL and netlist power-analysis tools such as Power Artist, PrimeTime PX, or equivalent.
Familiarity with CPU microarchitecture and its power impact, including CPU pipeline design, out-of-order execution, cache hierarchy, and branch prediction.

Nice To Haves

Proficiency using AI tools for automation and data analysis.
Experience with DVFS, clock gating, power gating, and multi-voltage-domain design.
Knowledge of lab instrumentation for power measurement.
Strong communication skills for cross-team technical discussions.

Responsibilities

Model and estimate CPU power at the C-model, RTL, and netlist stages using industry-standard tools.
Identify power inefficiencies and drive design improvements with architects, RTL designers, and physical design engineers.
Create targeted power-characterization tests, including peak-power and di/dt stress patterns, for simulation and silicon.
Set up power-measurement equipment and measure CPU power and performance in the lab.
Correlate silicon results with pre-silicon estimates to refine power models.
Collaborate with engineering disciplines to optimize power efficiency without compromising performance.