Senior System Power Architect

Lattice Semiconductor•San Jose, CA

21h•$220,000

About The Position

The Senior System Power Architect drives power analysis and low-power optimization across Lattice FPGA hardware and software. The role involves designing low-power feature specifications, algorithms, and methodologies, and collaborating with hardware, software, marketing, and applications teams. The architect develops chip-level power estimation models, establishes power-aware RTL methodology, and leads and mentors junior engineers across distributed teams.

Requirements

BS, MS, or PhD in EE, CE, CS, or a related field, with relevant experience of 8+ years for BS, 6+ years for MS, or 3+ years for PhD.
Strong knowledge of low-power design techniques.
Deep expertise in RTL and gate-level power analysis and optimization, as well as power-aware synthesis and place-and-route.
Hands-on experience with industry power and timing tools such as PrimePower, PrimeTime, SpyGlass, Joules, Voltus, or PowerArtist.
Strong knowledge of static timing analysis (STA) and power/timing ECO flows.
Proficiency in C/C++ and Python.
Strong written and verbal communication skills.
Ability to drive cross-functional alignment.

Nice To Haves

Knowledge of FPGA architecture, design flows, and use cases.

Responsibilities

Define low-power feature specifications, user flows, and algorithms, and align software, marketing, and applications teams.
Drive power-performance analysis to influence hardware and software roadmaps.
Develop chip-level power estimation models covering dynamic, static, clock, memory, and I/O power, and correlate models with simulations and silicon.
Establish power-aware RTL methodology.
Develop power and competitive benchmarks.
Lead and mentor junior engineers across distributed teams.