RTL core/processor Microarchitecture Engineer

Qualcomm • Austin, TX

5d • $101,400 - $152,200

About The Position

Qualcomm Technologies, Inc. is seeking an RTL engineer to join its Hexagon processor microarchitecture team. The role contributes to the design and development of next-generation AI and modem cores, including processors supporting Qualcomm’s AI Engine and AI, mobile, automotive, IoT, and edge computing workloads. The work focuses on high-performance, low-power, energy-efficient CPU and AI cores and hardware-software co-optimization for neural network inference.

The engineer owns and drives RTL design and microarchitecture development, collaborates with architecture, verification, physical design, and software teams, and works through the design cycle to optimize performance, power, and area and resolve timing, area, and functional issues. The position applies instruction set architecture knowledge to microarchitecture decisions and supports AI and signal processing workloads.

Requirements

• Master’s degree in Computer Engineering, Electrical Engineering, or a related field.
• At least 1 year of experience in processor architecture or RTL design.
• Bachelor’s degree in Science, Engineering, or a related field is also listed under Minimum Qualifications.
• Strong understanding of CPU microarchitecture, including instruction pipelines, out-of-order execution, branch prediction, load/store units, memory hierarchy, cache coherence and ordering, and multithreaded and multicore systems.
• Proficiency in RTL design using Verilog/SystemVerilog.
• Familiarity with low-power design techniques and synthesis/timing closure.
• Excellent communication and teamwork skills.

Nice To Haves

• Experience with AI accelerators, DSPs, or NPUs is a strong plus.

Responsibilities

• Own and drive RTL design and microarchitecture development for high-performance, low-power CPU and AI cores.
• Collaborate with architecture, verification, physical design, and software teams to deliver production-quality RTL.
• Contribute to performance, power, and area optimization, including clock gating, power domains, and low-power techniques.
• Analyze and resolve timing, area, and functional issues across the design cycle.
• Apply instruction set architecture knowledge to guide microarchitecture decisions and support AI and signal processing workloads.
• Work with AI software and compiler teams on hardware-software co-optimization for neural network inference.

Benefits

• Competitive annual discretionary bonus program.
• Opportunity for annual RSU grants; employees on sales-incentive plans are not eligible for the annual bonus.
• Competitive benefits package designed to support employees at work, at home, and at play.

What This Job Offers

• Job Type: Full-time
• Career Level: Entry Level