R&D Engineer Physical Design

Broadcom • San Jose, CA

3d • $143,800 - $230,000

About The Position

Broadcom is seeking an experienced STA and Timing Closure Engineer to lead static timing analysis and signoff execution for high-complexity, multi-GHz System-on-Chip (SoC) architectures on advanced FinFET and GAA process nodes (5nm, 3nm, and 2nm). The role owns full-chip and block-level timing closure across complex multi-voltage, multi-frequency domains, with the goal of achieving first-pass silicon success while optimizing Performance, Power, and Area (PPA).

The position works closely with physical design teams and interfaces with foundry characterization data to execute timing closure and signoff verification. The annual base salary range is USD 143,800 to USD 230,000. Eligible employees may receive a discretionary annual bonus, a new-hire equity grant, and annual equity awards, subject to applicable plan documents and award agreements.

Broadcom offers medical, dental, and vision plans; 401(k) participation with company matching; an Employee Stock Purchase Program (ESPP); an Employee Assistance Program (EAP); company-paid holidays; paid sick leave and vacation time; and leaves of absence in accordance with applicable laws, including Paid Family Leave.

Requirements

• Bachelor of Science in Electrical Engineering and 12 or more years of related experience, or a Master of Science in Electrical Engineering and 10 or more years of related work experience.
• Experience in static timing analysis and timing closure for complex SoC architectures.

Responsibilities

• Architect, configure, and maintain rigorous multi-mode, multi-corner (MMMC) STA environments across hundreds of process, voltage, temperature (PVT), and operational modes.
• Develop and audit constraints for complex clock structures.
• Collaborate closely with physical design teams to analyze timing bottlenecks and execute the timing closure loop.
• Generate precise engineering change orders (ECOs), both automated and functional/manual.
• Validate timing margins against foundry standard-cell, macro, and interface IP characterization data.
• Run strict signoff audits to ensure there are no critical timing violations prior to tapeout.

Benefits

• Discretionary annual bonus
• Competitive new-hire equity grant and annual equity awards, subject to applicable plan documents and award agreements
• Medical, dental, and vision plans
• 401(k) participation with company matching
• Employee Stock Purchase Program (ESPP)
• Employee Assistance Program (EAP)
• Company-paid holidays
• Paid sick leave and vacation time
• Paid Family Leave and other leaves of absence in accordance with applicable laws

What This Job Offers

• Job Type: Full-time
• Career Level: Senior