R&D Engineer Physical Design

Broadcom • San Jose, CA

2d

About The Position

Broadcom is seeking an experienced STA and Timing Closure Engineer to lead static timing analysis and signoff execution for high-complexity, multi-GHz System-on-Chip (SoC) architectures on advanced FinFET and GAA nodes (5nm, 3nm, and 2nm). The role owns end-to-end full-chip and block-level timing closure across complex multi-voltage and multi-frequency domains, with the goal of achieving first-pass silicon success while maximizing Performance, Power, and Area (PPA) metrics.

Requirements

• Bachelor of Science degree in Electrical Engineering and 12 or more years of related experience, or a Master of Science degree in Electrical Engineering and 10 or more years of related work experience.

Responsibilities

• Architect, configure, and maintain rigorous multi-mode, multi-corner (MMMC) STA environments across hundreds of process, voltage, temperature (PVT), and operational modes.
• Develop and audit constraints for complex clock structures.
• Collaborate with physical design teams to analyze timing bottlenecks.
• Generate precise ECOs, both automated and functional/manual.
• Validate timing margins against foundry standard cell, macro, and interface IP characterization data.
• Run strict signoff audits to ensure there are no critical timing violations before tapeout.

Benefits

• Discretionary annual bonus
• Competitive new-hire equity grant and annual equity awards
• Medical, dental, and vision plans
• 401(k) participation with company matching
• Employee Stock Purchase Program (ESPP)
• Employee Assistance Program (EAP)
• Company-paid holidays
• Paid sick leave and vacation time
• Paid family leave and other leaves of absence in accordance with applicable laws

What This Job Offers

• Job Type: Full-time
• Career Level: Senior