Process Integration and Defect reduction Engineer

Intel Corporation•Rio Rancho, NM

1d•$76,390 - $125,660•Onsite

About The Position

The New Mexico Silicon Manufacturing (NM Si Mfg) Yield Department is seeking Process Integration and Defect Reduction Engineers to support interconnect and advanced packaging semiconductor fabrication for Intel's Foveros and EMIB technologies. In this role, you will collaborate across multiple Yield Department functions, including Process Integration, Defect Reduction, Quality and Reliability, Device Analysis, and Yield Analysis. Engineers in this organization are responsible for sustaining process health as products transition from development into high-volume manufacturing (HVM), while driving improvements in yield, quality, reliability, cost, and manufacturability. This position offers the opportunity to solve complex technical challenges, leverage data to drive decisions, and influence the successful ramp and production of next-generation semiconductor technologies. The NM Si Mfg Yield team is looking for engineers who thrive in a fast-paced manufacturing environment and enjoy problem solving, data analysis, and cross-functional collaboration. In this role, you will design and conduct experiments, analyze large datasets, and optimize fabrication processes to improve device performance and manufacturing outcomes.

Requirements

Must possess a Bachelor's or Master's degree in Chemical Engineering, Electrical Engineering, Mechanical Engineering, Materials Science, Microelectronics Engineering, Chemistry, Physics, or a related technical field.

Nice To Haves

Creative problem-solving skills with the ability to develop innovative technical solutions.
Strong analytical and data interpretation capabilities, including working with large and complex datasets.
Knowledge of inline defect detection methodologies and their impact on process performance and yield.
Effective project management skills, including planning, execution, and risk assessment.
Understanding of process control monitoring strategies and statistical methods for detecting process variation.
Ability to influence and collaborate effectively across technical and manufacturing organizations.
Strong written and verbal communication skills.
Experience working in a high-performing team environment with demonstrated leadership, teamwork, and problem-solving skills.
Fundamental understanding of semiconductor manufacturing process flow.
Experience applying Design of Experiments (DOE) methodologies.
Experience supporting High-Volume Manufacturing (HVM) environments.
Experience with data analysis and statistical process control tools such as JMP, SQL, and PCS.
Knowledge of Statistical Process Control (SPC), process capability, specification limits, and process variation analysis.
Strong written and verbal communication skills.
Experience with semiconductor yield improvement, defect reduction, process integration, or advanced packaging technologies.

Responsibilities

Develop and execute experiments to optimize and characterize semiconductor manufacturing processes.
Analyze process, defect, and yield data to identify trends, correlations, and opportunities for improvement.
Monitor inline defectivity, parametric performance, and end-of-line yield metrics to ensure process stability.
Investigate process excursions, determine root causes, and drive corrective actions.
Manage and control technology change implementation within the manufacturing environment.
Partner with cross-functional teams to improve yield, quality, reliability, productivity, and cost.
Support the transfer of new technologies and products from Technology Development (TD) into High-Volume Manufacturing (HVM).
Develop and implement process control strategies to identify and respond to out-of-control conditions.
Lead and participate in projects focused on defect reduction, yield improvement, and manufacturing efficiency.
Respond to quality events and ensure timely disposition support across all phases of the product lifecycle.