Defect Reduction Engineer

Samsung Electronics•Austin, TX

1d•$76,000 - $145,000•Onsite

About The Position

As a Defect Reduction Engineer, the candidate will support defect control and reduction work in a high volume 24x7 manufacturing environment, on purpose to achieve yield and performance goals.

Requirements

Requires a Bachelor's degree in Electrical, Chemical, Mechanical Engineering, Material Science, Chemistry, Physics or related technical fields.
Requires a minimum of 10 years of Semiconductor process engineering experience in defect monitor and reduction.
Working knowledge in SPC and DOE methodology is required
Excellent communication skills (written, verbal and presentation) and experience as a contributing member of cross functional teams is required
Ability to meet deadlines, schedules and commitments is required.

Nice To Haves

Experience in leading logic technology (45nm or below) development is strongly preferred.
Relevant experience in advanced defect inspection and review tools (bright field, dark field, e-beam, Vis-edge…etc) is strongly preferred.
Knowledge of Klarity Defect (or similar) software and its application in a semiconductor processing environment is useful.
Strong data mining, troubleshooting skills and an energetic self-starter personality preferred.
Strong organizational skills to manage multiple tasks and able to react to shifting priorities.

Responsibilities

Supporting New Product Introduction (NPI) as the Defect Reduction representative: attending meetings, presenting inline inspection strategy & methodology, supporting GPM set up, spec audits, and comparison, evaluating unit part process changes and tool spreads in terms of inline and NPW defectivity data.
Performing fab process/tool trend data and correlation analysis to identify dog tools, trace defects to root cause, and rapidly take action to prevent inline process excursions.
Working cross-functionally with YE/PIE/UP to evaluate defect data on BKMs & projects, excursion monitoring & control, SWLY reduction.
Establishing FCC (Failed Chip Count) and trend monitoring plans for new technology introductions and ramps (14nm & foundry) and existing legacy production nodes (45nm/32nm/28nm) in order to achieve yield and performance goals, and support on weekly module meetings & activities.
Responding to foundry customer requests and delivering the data & analysis to meet expectation.
Supporting new technology and process transfer projects from Samsung HQ (South Korea).