Defect Reduction Engineer

Samsung Electronics•Austin, TX

8d•$76,000 - $120,000•Onsite

About The Position

We are seeking a highly skilled and experienced Defect Reduction Engineer to drive yield enhancement and process stability within our advanced semiconductor fabrication environment. This critical role focuses on the identification, analysis, and elimination of defect sources across multiple technology nodes, ranging from legacy production to leading-edge 14nm and foundry processes. The successful candidate will serve as the primary subject matter expert in defectivity, ensuring that our manufacturing processes meet the highest standards of quality and performance. The core of this position involves leading Defect Reduction strategies for New Product Introduction (NPI), where you will independently define inline inspection methodologies and establish robust monitoring plans. You will be responsible for performing deep-dive correlation analyses of tool trend data to identify underperforming equipment and rapidly mitigate process excursions. By leveraging advanced inspection tools (Bright Field, Dark Field, E-beam) and analytical platforms like Klarity, you will trace defects to their root cause and implement permanent corrective actions. Collaboration is central to this role. You will work autonomously yet synchronously with cross-functional teams, including Yield Enhancement (YE), Process Integration (PIE), and Unit Process (UP) engineering, to establish Best Known Methods (BKMs) and drive the reduction of "Same Wafer, Last Year" (SWLY) defectivity. Additionally, you will act as a key technical liaison for foundry customers and support the seamless transfer of new technologies from Samsung HQ in South Korea.

Requirements

Bachelor’s degree in Electrical, Chemical, Mechanical Engineering, Material Science, Chemistry, Physics, or a related technical field.
Minimum of 5 years of proven experience in semiconductor process engineering, specifically specializing in defect monitoring, reduction, process integration, or yield engineering preferred
Strong preference for candidates with a track record in leading-edge logic technology development (14nm or below).
Deep understanding of semiconductor manufacturing equipment (e.g., Lithography, Etch, CMP) to effectively link defects to tool-specific root causes.
Proficiency in advanced defect inspection and review tools (e.g., Bright Field, Dark Field, E-beam, Vis-edge).
Expert-level application of SPC and DOE methodologies to stabilize processes.
Proficiency in Klarity Defect or similar advanced analytical platforms for defect classification and trend analysis.
Strong data mining and troubleshooting capabilities to resolve chronic and ad-hoc yield killers independently.
Demonstrated project management success in driving solutions for complex technical problems from identification to closure.
Ability to manage multiple high-priority tasks in a fast-paced environment with minimal supervision.
Excellent communication and presentation skills, with a proven ability to influence cross-functional teams (YE, PIE, UP).
A self-starter mindset with a commitment to meeting strict deadlines and production schedules.

Responsibilities

Serves as the primary representative for defect reduction during NPI, defining how parts will be inspected (strategy & methodology).
Handles Global Process Management (GPM) setup, conducts specification audits, and performs comparisons to ensure standards are met.
Evaluates how changes in unit processes or the distribution of parts across different tools (tool spread) affect inline and Non-Product Wafer (NPW) defectivity.
Monitors fab process and tool data to identify "dog tools" (underperforming equipment).
Performs correlation analysis to trace defects back to their root cause, enabling rapid response to prevent widespread process excursions.
Works with Yield Enhancement (YE), Process Integration Engineering (PIE), and Unit Process (UP) teams.
Evaluates defect data to establish Best Known Methods (BKMs), monitors excursions, and focuses on SWLY (Same Wafer, Last Year/Lot) reduction to improve consistency.
Establishes Failed Chip Count (FCC) and trend monitoring plans.
Manages a wide range of technology nodes, including: Advanced Nodes: 14nm and Foundry processes. Legacy Nodes: 45nm, 32nm, and 28nm.
Leads/supports weekly module meetings to ensure yield and performance targets are achieved.
Acts as a technical point of contact for foundry customers, providing the necessary data and analysis to meet client expectations.
Supports the transfer of new technologies and processes originating from Samsung HQ in South Korea to local sites.