Process integration and Defect Reduction Engineer

Intel Corporation•Rio Rancho, NM

1d•$120,860 - $170,630•Onsite

About The Position

The New Mexico Silicon Manufacturing (NM Si Mfg) Yield Department is seeking Process Integration and Defect Reduction Engineers to support backend interconnect and advanced packaging semiconductor fabrication. These roles support Fab 11X, with a focus on Intel's Foveros and EMIB technologies. In this position, you will partner with teams across Yield Engineering, including Process Integration, Defect Reduction, Quality and Reliability, Device Analysis, and Yield Analysis. You will be responsible for sustaining process health as products transition from development into high-volume manufacturing (HVM) while driving improvements in yield, quality, reliability, cost, and manufacturability. The NM Si Mfg Yield team is looking for engineers who are passionate about problem-solving, data analysis, and cross-functional collaboration. You will design and execute experiments, analyze process and yield data, and optimize manufacturing processes to reduce defects and improve overall product performance. Responsibilities include managing technology change introductions, monitoring inline defectivity and parametric performance, investigating process excursions, identifying root causes, and implementing corrective actions. In addition, you will support the transfer of new products from Technology Development (TD) into manufacturing and ensure readiness for successful high-volume production.

Requirements

Bachelor's or Master's degree in Chemical Engineering, Electrical Engineering, Mechanical Engineering, Materials Science, Microelectronics Engineering, Chemistry, Physics, or a related technical field.
3+ years of experience in the semiconductor industry.
Strong teamwork, leadership, problem-solving, and prioritization skills in a high-performance environment.
Excellent written and verbal communication skills.
The ability to present technical information clearly and effectively to audiences with varying levels of technical expertise.
The ability to work independently with minimal supervision while effectively managing multiple priorities.
Experience leading factory-level projects and delivering results in a timely manner.
Strong project management skills, with the ability to execute roadmaps that drive improvements in yield, defect reduction, efficiency, and cost.
The ability to balance collaboration and critical thinking to drive data-based decisions and technical solutions.

Nice To Haves

3+ years of experience in process integration or defect reduction for backend interconnect or advanced packaging processes.
3+ years of experience applying Design of Experiments (DOE) methodologies.
3+ years of experience in data analysis and statistical process control using tools such as JMP, SQL, PCS, or similar platforms.
Strong understanding of semiconductor manufacturing process flow and advanced packaging technologies.
Knowledge of process capability, specification limits, statistical variation, and process control methodologies.

Responsibilities

Sustaining process health as products transition from development into high-volume manufacturing (HVM)
Driving improvements in yield, quality, reliability, cost, and manufacturability
Designing and executing experiments
Analyzing process and yield data
Optimizing manufacturing processes to reduce defects and improve overall product performance
Managing technology change introductions
Monitoring inline defectivity and parametric performance
Investigating process excursions
Identifying root causes
Implementing corrective actions
Supporting the transfer of new products from Technology Development (TD) into manufacturing
Ensuring readiness for successful high-volume production