About The Position

Neurophos is seeking a Systems Engineer to own the quantitative, end-to-end performance model of its optical vector-matrix multiplication (OVMM) engine. The role leads modeling, analysis, and architectural definition for high-speed communication and signal-processing systems, including building and maintaining link and power budgets; quantifying optical, analog, and digital impairments; developing mathematical and behavioral models; and defining hardware and algorithmic techniques needed to meet system-level performance targets. The engineer will analyze trade-offs among accuracy, throughput, and power as the architecture evolves, primarily through system-level simulations and the development of defensible performance allocations. The role owns the signal-path architecture that converts digital data into an optical signal and back, spanning digital signal processing, D/A and A/D conversion, and surrounding analog and optical signal conditioning on both transmit and receive sides. It also owns the reference behavioral model of the full TX–channel–RX path and the end-to-end optical and electrical link/power budget, correlating model predictions with laboratory and silicon measurements. The position is full-time and onsite in Austin, Texas, and reports to the Chief Systems Engineer.

Requirements

  • MS or PhD in Electrical Engineering, Applied Physics, or a closely related field, emphasizing communication theory, signal processing, or mixed-signal systems.
  • At least 7 years of professional experience in communication systems architecture, link-budget/signal-chain modeling, or performance modeling of optical or high-speed electrical communication systems. Time spent pursuing a PhD beyond the MS counts toward this experience.
  • Deep knowledge of modulation formats, equalization, synchronization and estimation, quantization effects, and coding-gain concepts, including how they factor into an end-to-end performance budget.
  • Expert-level proficiency in Python (NumPy/SciPy) and/or MATLAB/Simulink for behavioral modeling, Monte Carlo simulation, and statistical/time-domain analysis.
  • Experience with optical or high-speed electrical link budgets, including allocating impairments across components and predicting system-level impact.
  • Excellent written and verbal communication skills, with credibility to negotiate requirements with implementation teams and defend an architectural position to technical leadership.

Nice To Haves

  • Demonstrated ownership of system architecture definition.
  • Experience with coherent or direct-detection architectures, or high-speed SerDes/networking standards such as Ethernet, PCIe, or OIF-CEI.
  • System-level modeling of high-speed data converters (ADC/DAC), including quantization, sampling, and multi-device synchronization effects.
  • Familiarity with Cadence Virtuoso and Spectre sufficient to validate behavioral models against circuit-level simulation.
  • Hands-on laboratory characterization or silicon/system bring-up experience.
  • Familiarity with photonic integrated circuits, silicon photonics, or optical transceiver systems.
  • Experience carrying a signal-path architecture across multiple product generations.

Responsibilities

  • Own and define the architecture of the high-speed communication and signal-processing system from digital data stream to optical signal and back, including DSP, D/A and A/D conversion, and transmit- and receive-side analog/optical signal conditioning.
  • Define the signal-path blocks and processing stages and specify requirements for each; negotiate block-level requirements with photonic and mixed-signal implementation teams.
  • Own and maintain the end-to-end optical and electrical link/power budget, keeping it synchronized with as-designed and as-measured hardware as the architecture evolves.
  • Build and maintain a reference behavioral model of the full TX–channel–RX signal path, capturing optical, analog, quantization, and algorithmic effects at a fidelity appropriate for architecture decisions and requirements allocation.
  • Allocate NMSE/SNR/SNDR targets across optical, analog, quantization, and algorithmic domains, and update allocations as component and architectural choices change.
  • Characterize and model optical, analog, and digital impairments—including noise, distortion, jitter, quantization effects, crosstalk, mismatch, and nonlinearity—and quantify their impact on system-level accuracy.
  • Analyze the effects of TX/RX channel configurations and architectural options on TOPS, TOPS/W, and latency; balance complexity, risk, and time-to-market for proposed solutions.
  • Develop and run Monte Carlo, corner, and time-domain simulations to quantify design margin and manufacturing robustness.
  • Correlate model predictions with laboratory and silicon measurements; investigate discrepancies and refine the architecture, model, and allocations.
  • Represent the system architecture in roadmap and planning discussions.
  • Provide predicted and measured quantitative performance data to support other Neurophos efforts, including customer-facing technical discussions.
  • Support calibration accuracy-budget definition with sensitivity analysis.
  • Collaborate with analog, photonic, digital, and software engineers to maintain consistency between subsystem designs, the architecture, and performance targets.
  • Mentor engineers in system modeling, communication theory, and architecture/trade-study methodology.
  • Contribute to intellectual property creation, including invention disclosures and patents.

Benefits

  • 100% coverage of base health plan premiums for the employee and dependents, plus HSA contributions.
  • Unlimited PTO.
  • 401(k) matching.
  • Stock option opportunities.
  • Voluntary benefits including Dental, Vision, Life, Hospital, Critical Illness, and Accident insurance.
  • Personalized benefit-plan choices, with cash back for plans not selected.
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