Hardware Engineer, Performance Modeling

Normal Computing Corporation • Palo Alto, CA

5d

About The Position

Normal Computing is an applied AI company building foundational hardware and software for the semiconductor industry, AI infrastructure, and systems in partnership with advanced institutions. The company operates across New York City, Silicon Valley (Mountain View), London, Copenhagen, and Seoul.

As a Performance Modeling Engineer, you will build the transaction-level model (TLM) for Normal’s physics-inspired ASICs. This model sits between RTL and the rest of the modeling stack and is used by architecture and verification teams. You will own the path from RTL to numerical performance results, correlate the TLM against RTL, FPGA prototypes, and synthesis results, and convert those results into calibrated latency, bandwidth, and energy parameters for kernel-level models. You will work closely with architecture, hardware design, and design verification (DV) teams to refine the end-to-end system.

The role applies performance-modeling expertise to a new architecture and to AI workloads. Normal Computing aims to build a next-generation system with a 100–1000× improvement in AI inference.

Requirements

• At least 5 years of experience in performance modeling at a major semiconductor company.
• Demonstrated proficiency in understanding architectures and transforming them into performant modeling code.
• Experience using various modeling techniques and languages.
• Excellent written and spoken communication skills.

Nice To Haves

• Experience with AI acceleration hardware.
• Experience with architecture-level modeling and cost tools such as AccelForge, Timeloop/Accelergy, CACTI, McPAT, or gem6.
• Experience with design verification methodology.
• Hands-on use of LLMs or agentic tools in development workflows.
• Exposure to analog, mixed-signal, or unconventional compute.
• Experience with memory interfaces such as LPDDR, HBM, or DDR, and other I/O.

Responsibilities

• Build and maintain a cycle-accurate approximate transaction-level model of compute tiles, the memory hierarchy, and interconnect using an appropriate language such as SystemC, C++, or Python.
• Ensure the model simulates real workloads efficiently and is accurate enough to inform production design decisions.
• Translate TLM and RTL results, combined with physical-design information, into calibrated parameters such as latency, bandwidth, energy, utilization, and occupancy for end-to-end system-level AI workload performance prediction.
• Provide the TLM as a golden reference model for design verification, including transaction-level scoreboards and performance checks.
• Work with DV and RTL teams to ensure RTL achieves the desired behavior and that the TLM and RTL reflect one another.
• Plan modeling work against the hardware roadmap.
• Run sensitivity studies on hardware parameters, including buffer sizes, interface widths, scheduling policies, and bus configurations, and provide clear recommendations to architecture and hardware teams.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Education Level: No Education Listed