Hardware Engineer, Performance Modeling

Normal Computing Corporation • Palo Alto, CA

4d

About The Position

Normal Computing is hiring a Performance Modeling Engineer to build the transaction-level model (TLM) for its physics-inspired ASICs. The TLM sits between RTL and the rest of the modeling stack and supports both architecture and verification teams. The engineer will own the path from RTL to numerical performance results by correlating the TLM against RTL, FPGA prototypes, and synthesis results, then producing calibrated latency, bandwidth, and energy parameters for kernel-level models. The role involves working closely with architecture, hardware design, and design verification teams to refine the end-to-end system. The position focuses on applying performance-modeling expertise to a novel computing architecture and AI workloads.

Requirements

• At least 5 years of experience in performance modeling at a major semiconductor company.
• Demonstrated proficiency in understanding architectures and translating them into performant modeling code.
• Experience using various modeling techniques and languages.
• Excellent written and spoken communication skills.

Nice To Haves

• Experience with AI acceleration hardware.
• Experience with architecture-level modeling and cost tools such as AccelForge, Timeloop/Accelergy, CACTI, McPAT, or gem5.
• Experience with design verification methodology.
• Hands-on use of LLMs or agentic tools in development workflows.
• Exposure to analog, mixed-signal, or unconventional compute.
• Experience with memory interfaces such as LPDDR, HBM, and DDR, and other I/O.

Responsibilities

• Build and maintain a cycle-accurate approximate transaction-level model of compute tiles, memory hierarchy, and interconnect using SystemC, C++, Python, or an appropriate language.
• Ensure the model simulates real workloads quickly and accurately enough to inform production design decisions.
• Correlate the TLM against RTL, FPGA prototypes, and synthesis results.
• Translate TLM and RTL results, combined with physical design, into calibrated parameters such as latency, bandwidth, energy, utilization, and occupancy for end-to-end system-level AI workload performance prediction.
• Provide the TLM as a reference golden model for design verification, including transaction-level scoreboards and performance checks.
• Work with the design verification and RTL teams to ensure RTL produces the desired behavior and that the TLM and RTL reflect one another.
• Plan modeling work against the hardware roadmap.
• Run sensitivity studies on hardware parameters, including buffer sizes, interface widths, scheduling policies, and bus configurations, and provide clear recommendations to architecture and hardware teams.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Education Level: No Education Listed