Principal Systems Engineer, Signal-Path Performance & Modeling

Neurophos • Austin, TX

12d • $245,000 - $285,000 • Onsite

About The Position

Neurophos is seeking a Principal Systems Engineer to own the quantitative, end-to-end performance model of its optical vector-matrix multiplication (OVMM) engine. The role leads modeling, analysis, and architectural definition for high-speed communication and signal-processing systems. It builds and maintains link and power budgets, quantifies impairments across optical, analog, and digital domains, develops mathematical and behavioral models, defines hardware and algorithmic techniques for system-level performance targets, and evaluates tradeoffs among accuracy, throughput, and power as the architecture evolves.

The position focuses primarily on system-level simulations and translating their results into performance allocations that other teams can use as design targets. The engineer will own the signal-path architecture from digital input through optical transmission and back, including DSP, digital-to-analog and analog-to-digital conversion, and transmit- and receive-side signal conditioning. The role is full-time and onsite in Austin, Texas, and reports to the Chief Systems Engineer.

Requirements

• MS or PhD in Electrical Engineering, Applied Physics, or a closely related field, with emphasis on communication theory, signal processing, or mixed-signal systems.
• At least 7 years of professional experience in communication systems architecture, link-budget or signal-chain modeling, or performance modeling of optical or high-speed electrical communication systems; time pursuing a PhD beyond an MS counts toward this experience.
• Deep knowledge of modulation formats, equalization, synchronization and estimation, quantization effects, and coding-gain concepts, and how they factor into an end-to-end performance budget.
• Expert-level proficiency in Python (NumPy/SciPy) and/or MATLAB/Simulink for behavioral modeling, Monte Carlo simulation, and statistical or time-domain analysis.
• Experience with optical or high-speed electrical link budgets, including allocating impairments across components and predicting system-level impact.
• Excellent written and verbal communication, including the credibility to negotiate requirements with implementation teams and defend an architectural position to technical leadership.

Nice To Haves

• Demonstrated ownership of system architecture definition.
• Experience with coherent or direct-detection architectures, or high-speed SerDes/networking standards such as Ethernet, PCIe, or OIF-CEI.
• System-level modeling of high-speed data converters (ADC/DAC), including quantization, sampling, and multi-device synchronization effects.
• Familiarity with Cadence Virtuoso and Spectre sufficient to validate behavioral models against circuit-level simulation.
• Hands-on laboratory characterization or silicon/system bring-up experience.
• Familiarity with photonic integrated circuits, silicon photonics, or optical transceiver systems.
• Experience carrying a signal-path architecture across multiple product generations.

Responsibilities

• Own and define the architecture of the high-speed communication and signal-processing system converting digital data into an optical signal and back, including DSP, D/A and A/D conversion, and transmit- and receive-side analog/optical conditioning.
• Define the system blocks and processing stages, specify their requirements, and negotiate block-level requirements with photonic and mixed-signal implementation teams.
• Own and maintain the end-to-end optical and electrical link and power budget, keeping it aligned with as-designed and as-measured hardware as the architecture evolves.
• Build and maintain the reference behavioral model of the full TX–channel–RX signal path, capturing optical, analog, quantization, and algorithmic effects for architecture decisions and requirements allocation.
• Allocate NMSE/SNR/SNDR targets across optical, analog, quantization, and algorithmic domains, and update allocations as components and architecture change.
• Characterize and model optical, analog, and digital impairments, including noise, distortion, jitter, quantization effects, crosstalk, mismatch, and nonlinearity, and quantify their impact on system-level accuracy.
• Analyze the impact of TX/RX channel configurations and architectural options on TOPS, TOPS/W, and latency; balance solution complexity, risk, and time-to-market.
• Develop and run Monte Carlo, corner, and time-domain simulations to quantify design margin and manufacturing robustness.
• Correlate model predictions with laboratory and silicon measurements; investigate discrepancies and refine the architecture, model, and allocations.
• Represent the system architecture in roadmap and planning discussions.
• Provide predicted and measured quantitative performance data to support other Neurophos efforts, including customer-facing technical discussions.
• Support calibration accuracy-budget definition with sensitivity analysis.
• Collaborate with analog, photonic, digital, and software engineers to keep subsystem designs consistent with the architecture and performance targets.
• Mentor engineers in system modeling, communication theory, and architecture and trade-study methodology.
• Contribute to intellectual property creation, including invention disclosures and patents.

Benefits

• 100% coverage of base health plan premiums for the employee and dependents, plus HSA contributions.
• Unlimited PTO.
• 401(k) matching.
• Stock option opportunities.
• Voluntary dental, vision, life, hospital, critical illness, and accident insurance.
• Personalized benefits plans, with the option to take cash back for plans not selected.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior