Principal SoC Design Engineer / SoC Lead

Neurophos • Austin, TX

2d • Onsite

About The Position

Neurophos is developing a novel AI compute architecture using silicon photonics to overcome the power limitations of traditional digital solutions. Our approach uses optical cells for matrix multiplications, offering significantly higher energy efficiency and performance for large-scale AI inference. We have a world-class team and have recently secured $110M in Series A funding. We are seeking a Principal SoC Design Engineer / SoC Lead to own the integration of the full chip or major modules/subsystems. This role requires making cross-domain technical decisions across DFT, power, timing, and interconnect architecture, working closely with various design teams to resolve system-level tradeoffs. You will also play a key role in scaling the design organization by hiring and mentoring engineers.

Requirements

• Principal-level (or equivalent) technical leadership experience at a semiconductor or systems company, with multiple full-chip tapeouts.
• Demonstrated breadth across domains: for example, you've closed timing on a block and argued interconnect architecture in the same design cycle.
• Deep experience in at least one of: CPU design, or high-speed interconnect / data-fabric design.
• Experience with advanced process nodes, high-bandwidth I/O, and large, physically big subsystem or full-chip designs.

Nice To Haves

• Cadence toolchain experience.
• Comfortable being evaluated as either an individual-contributor technical leader or a people manager; we're open to either path for the right person.
• Familiarity with AI/ML accelerator or large-scale compute workloads, though not required.
• Familiarity with AI-assisted EDA flows in the Cadence toolchain (e.g., Cerebrus) for synthesis, timing closure, or verification.

Responsibilities

• Lead integration of the full chip, or a major module/subsystem, including ownership of top-level integration flows.
• Make and own cross-domain technical decisions spanning system functionality, DFT, power, timing, and interconnect/data-fabric architecture.
• Partner across microarchitecture, RTL, physical design, verification, and DFT to resolve system-level tradeoffs.
• Go deep on any domain when needed, staying hands-on with the flow at every level.
• Help scale the design org: hire, mentor, and grow engineers across specialty domains (subsystem roles are open now and will continue to open).
• Represent chip-level architecture in the context of advanced-node, high-speed, high-bandwidth, low-power, physically large designs.

Benefits

• 100% coverage of base health plan premiums for you and your dependents, plus HSA contributions.
• Unlimited PTO.
• 401(k) matching.
• Stock option opportunities.
• Full suite of voluntary benefits, including Dental, Vision, Life, Hospital, Critical Illness, and Accident insurance.
• Personalized Benefits: Choose the plans that fit your life and take the cash back for those that don’t.

What This Job Offers

• Job Type: Full-time
• Career Level: Principal
• Education Level: No Education Listed