Principal PLL Design Engineer

Celero Communications • Irvine, CA

19h

About The Position

The Principal PLL Design Engineer will architect and design phase-locked loops for next-generation optical transceivers, high-speed SerDes, and ADC/DAC systems at a fast-growing startup developing high-speed interconnect technology for AI. The role focuses on analog and mixed-signal PLL design, simulation, layout verification, laboratory bring-up, performance characterization, and system-level validation for integration into advanced transceiver technologies.

The engineer will evaluate PLL topology trade-offs to meet power, area, jitter, and frequency-range specifications; design transistor-level PLL building blocks; and address advanced-node challenges including self-heating, electromigration, VCO linearization, and device-level noise optimization. They will also supervise and verify layouts produced by layout engineers.

Requirements

• Master’s degree and/or PhD in Electrical Engineering or a related field.
• At least 5 years of relevant PLL design experience.
• Production-level tape-out experience.
• Extensive experience with advanced-node technologies, including 16nm/12nm, 7nm, 5nm, 3nm, or 2nm processes.
• Deep understanding of phase-noise analysis, VCO design, LDOs, and supporting PLL circuitry.
• Proficiency with Cadence Virtuoso, an electromagnetic simulator such as EMX or HFSS, and MATLAB for system-level modeling.
• Strong communication and documentation skills.

Responsibilities

• Evaluate trade-offs among PLL topologies, including integer-N, fractional-N, and all-digital/ADPLL, to meet power, area, jitter, and frequency-range specifications.
• Architect, design, and simulate analog/mixed-signal PLL building blocks at transistor level, including VCOs, charge pumps, dividers, PFDs, and loop filters.
• Address advanced-node challenges such as self-heating, electromigration, VCO linearization, and device-level noise optimization.
• Supervise and verify layouts produced by layout engineers, with attention to floorplanning, matching, and parasitic minimization.
• Bring up PLLs in the laboratory and conduct performance characterization using state-of-the-art lab equipment.
• Conduct system-level simulations and validation for PLL integration into advanced transceiver technologies.

What This Job Offers

• Job Type: Full-time
• Career Level: Principal