Principal Design Engineer

Micron Technology•San Jose, CA

1d•$181,000 - $308,000

About The Position

Micron Technology’s Non-Volatile Engineering Group develops NAND memory products. The Principal Design Engineer will lead architecture and design of the internal NAND datapath between the page buffer and IO, including wave-pipelined buses, flop-to-flop timing, FIFOs, dataline sensing, column repair, and clocking. The role uses AI daily to accelerate design, timing closure, and verification, and helps transition a simulation-only flow toward a STA-based semi-custom methodology. The engineer will set technical direction as a recognized technical leader.

Requirements

BS or MS in electrical engineering or a related field.
At least 8 years of experience in memory datapath, SRAM, or high-speed custom design.
Deep expertise in flop-to-flop and wave-pipelined timing closure, including setup/hold, skew, minimum/maximum delay, and PVT margin.
Experience in sense amplifier, dataline, or SRAM read/write design, including Monte Carlo/high-sigma verification.
Proven collaboration with layout on floorplanning, extraction, and post-layout timing correlation.
Daily hands-on AI use, with concrete examples of AI-based workflows (prompts, scripts, or agents) that improved productivity or design outcomes.

Nice To Haves

NAND, DRAM, or SRAM periphery experience, such as page buffer, column decoder, global data bus, or array-to-IO pipeline.
Memory repair and redundancy design experience, including understanding of impacts on yield, area, timing, and test time.
Experience with timing-adjustment techniques such as delay trims, DLL/DCC, or training, and with aging effects such as NBTI/HCI.
Experience building AI agents, LLM/RAG pipelines, or ML models for IC design, verification, or debug.
Sophisticated CMOS device physics, mismatch modeling (BSIM), and low-power techniques such as clock/power gating and leakage.
Solid understanding of STA and semi-custom flows combining custom and standard-cell logic.

Responsibilities

Define, design, and verify internal datapath blocks—including page-buffer-to-IO data buses, wave pipelines, FIFOs, SER/DES front ends, and datapath clocking—to meet bandwidth, timing, and power targets.
Architect and close wave-pipelined and flop-to-flop paths, including setup and hold, skew and jitter budgets, PVT delay tracking, and delay trims across PVT and aging.
Design dataline sense amplifiers and precharge/latch sensing, accounting for offset, Monte Carlo/high-sigma margin, coupling, and IR drop.
Design column repair, fuse/repair storage, and redundancy muxing without bandwidth or timing penalties; verify repair configurations with test, PE, and FW.
Use AI daily for RTL generation, scripting, and timing and waveform analysis; develop AI-processable specifications and checklists and build agents to automate timing, Monte Carlo, and repair-coverage checks.
Lead the move from SPICE-only closure to a semi-custom flow with characterized custom cells, SDC/STA sign-off, STA-to-SPICE correlation, and synthesis/APR/ECO flows.
Drive floorplanning, bus routing, and RC-aware delay matching with layout, and correlate post-layout timing.
Champion AI adoption and standard processes, define interface specifications with multifunctional teams, support silicon debug, and mentor engineers.