PLL Design Engineer

Apple • Cupertino, CA

2d

About The Position

As part of Apple’s Analog-Mixed/Signal group, the PLL Design Engineer develops frequency synthesizers for applications including Compute, SoC, SerDes, and Cellular technologies. The role contributes to the design of high-quality, innovative hard IPs for increasingly complex SoC/PHY designs and multiple projects operating on tight production schedules. The position calls for collaborative problem-solving, continual learning, and ownership of technical work.

Requirements

• BSEE.
• At least 10 years of relevant experience.
• Demonstrated proficiency in PLL/FLL and frequency-synthesis architecture and circuit design, including digital and analog approaches.
• Experience with DCO/VCO design, including ring-oscillator and LC designs, Fractional-N, SSC, and spur and jitter cancellation techniques.
• Good understanding of band gaps, bias circuits, op-amps, LDOs, feedback, and compensation techniques.
• Deep understanding of clocking fundamentals, phase noise, jitter analysis and budgeting, and feedback-loop dynamics.
• Skill in developing SystemVerilog models and performing behavioral simulations.
• Exceptional attention to detail and ability to understand problems and their systemic impacts.
• Outstanding teamwork, productivity, and scripting skills.

Nice To Haves

• RTL design and debugging experience.
• Experience using industry-standard design tools.
• A history of innovation and self-directed learning, demonstrated leadership skills, and a growth mindset.

Responsibilities

• Develop frequency synthesizers for Compute, SoC, SerDes, and Cellular applications.
• Contribute to innovative hard IP design for complex SoC/PHY designs and projects with tight production schedules.
• Develop SystemVerilog models and perform behavioral simulations to explore architectural performance and effects on loop dynamics.
• Design and debug RTL, as applicable.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior