PLL Design/ Integration Sr Staff Engineer

Advanced Micro Devices, Inc • San Jose, CA

2d

About The Position

AMD is seeking an experienced Staff Design Engineer to join its AECG Fabric team and lead or contribute to the design, integration, and characterization of Phase-Locked Loops (PLLs) for FPGA products across advanced process nodes. The role is part of AMD's Programmable Logic Group and its global Clock/PLL team, which develops programmable clocking solutions and methodologies for Adaptive Embedded Computing products.

The engineer will collaborate with functional architecture, programmable fabric, integration, and software teams to deliver clocking architectures, IP, tools, and flows. The position involves addressing complex clocking challenges in large SoCs and supporting PLL integration and post-silicon validation. The posting describes a need for a strong foundation in IC design and manufacturing, analog/digital IP integration, device physics, reliability, silicon processes, and packaging technologies. The role is not eligible for visa sponsorship.

Requirements

• Solid foundation in IC design and manufacturing.
• Experience with analog/digital IP integration, such as PLLs, LDOs, and phase interpolators.
• Experience with chip design, silicon processes, and packaging technologies.
• Strong understanding of device physics, reliability, and silicon chip manufacturing.
• Passion for adaptive computing architectures and post-silicon validation and characterization.
• Effective collaboration and communication across teams, with strong analytical and problem-solving skills.
• Willingness to learn and take initiative.
• Preferably an MS degree in electrical and electronics engineering; alternatively, a bachelor's degree with several years of relevant industry experience is acceptable.

Nice To Haves

• Experience designing fractional-N PLLs, all-digital PLLs (ADPLLs), and/or sub-sampling PLLs.
• Familiarity with analog building blocks such as LDOs, bias generators, and operational amplifiers.
• Background in digital design, digital verification, and SystemVerilog modeling.
• Knowledge of clock synthesis and recovery techniques, including PLLs, DLLs, and CDRs.

Responsibilities

• Architect and integrate analog/mixed-signal PLL building blocks, including VCOs, charge pumps, dividers, PFDs, and loop filters, as well as LDOs, phase interpolators, and high-speed dividers, into FPGA products across advanced process nodes.
• Lead integration of PLL topologies, including integer-N, fractional-N, and all-digital/ADPLL, to meet product-level power, area, jitter, and frequency-range specifications.
• Address advanced-node challenges including self-heating, electromigration, VCO linearization, and device-level noise optimization for product-level jitter optimization.
• Supervise and verify layouts produced by physical design engineers, ensuring floor planning, matching, and parasitic minimization.
• Bring up PLLs in the lab and conduct performance characterization using lab equipment.
• Conduct system-level simulations and validate PLL IP integration in an FPGA environment using Vivado or similar tools and flows.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior